From: Christoph Hellwig <hch@lst.de>
To: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: linux-mips@vger.kernel.org, chenhc@lemote.com,
paul.burton@mips.com, linux-kernel@vger.kernel.org, hch@lst.de
Subject: Re: [PATCH 1/2] MIPS: Define pgprot_dmacoherent according to coherentio status
Date: Mon, 13 Jan 2020 15:58:20 +0100 [thread overview]
Message-ID: <20200113145820.GA9817@lst.de> (raw)
In-Reply-To: <20200113140705.74605-1-jiaxun.yang@flygoat.com>
On Mon, Jan 13, 2020 at 10:07:04PM +0800, Jiaxun Yang wrote:
> For MIPS chips that support coherentio DMA, it's always safe
> to make DMA requests cached.
For DMA coherent devices pgprot_dmacoherent isn't even used, so this
doesn't make sense.
next prev parent reply other threads:[~2020-01-13 14:58 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-13 14:07 [PATCH 1/2] MIPS: Define pgprot_dmacoherent according to coherentio status Jiaxun Yang
2020-01-13 14:07 ` [PATCH 2/2] MIPS: Loongson64: Add dma iocoherency detection support Jiaxun Yang
2020-01-13 18:52 ` Paul Burton
2020-01-14 3:30 ` Jiaxun Yang
2020-01-13 14:58 ` Christoph Hellwig [this message]
2020-01-13 15:11 ` [PATCH 1/2] MIPS: Define pgprot_dmacoherent according to coherentio status Jiaxun Yang
2020-01-13 15:12 ` Christoph Hellwig
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