From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.6 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FAKE_REPLY_C,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5AD0C2D0DB for ; Tue, 28 Jan 2020 17:40:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8808D2465B for ; Tue, 28 Jan 2020 17:40:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1580233251; bh=xvhgfQQ5L9TDXPMISXTC3Sh2WZWsStbYQGl8G7pS4r8=; h=Date:From:To:Cc:Subject:In-Reply-To:List-ID:From; b=SfpbdoEH+o8BZpo4W3uexllgSWN6S+RGHzAnKNwnmOBNfoyZPP6M7JftksKT30o7g 3LF+qLjlBA0plng+QxcJH2dmViySXrxnEW+w4RHgR6kc93rmNtfleORyPLjzeqflVf Gc1pC1paamZiYsknJVb0DrElljEclkVVJSUC557o= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726233AbgA1Rkv (ORCPT ); Tue, 28 Jan 2020 12:40:51 -0500 Received: from mail.kernel.org ([198.145.29.99]:39818 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726066AbgA1Rku (ORCPT ); Tue, 28 Jan 2020 12:40:50 -0500 Received: from localhost (mobile-166-175-186-165.mycingular.net [166.175.186.165]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 9F8872465B; Tue, 28 Jan 2020 17:40:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1580233250; bh=xvhgfQQ5L9TDXPMISXTC3Sh2WZWsStbYQGl8G7pS4r8=; h=Date:From:To:Cc:Subject:In-Reply-To:From; b=Z8Xfe+ORuHL9ioZ5kXpem+/RFpCCtHqRtviOviDKDoaZvD+VfUjnIDGERZxa4zI3M mYO+oB/LvIezXMP/fbvV9ZtA0mgKvLgINK/eg0gZRL8KlYcnoBszzTIPzr4AtHNPwA h4fQ+s6Mpm9Mga/4+8MwrI9ucCkFeTqyH7b0iEgU= Date: Tue, 28 Jan 2020 11:40:47 -0600 From: Bjorn Helgaas To: Muni Sekhar Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: pcie: xilinx: kernel hang - ISR readl() Message-ID: <20200128174047.GA181400@google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Sat, Jan 18, 2020 at 07:16:14AM +0530, Muni Sekhar wrote: > On Thu, Jan 9, 2020 at 10:05 AM Bjorn Helgaas wrote: > > > > On Thu, Jan 09, 2020 at 08:47:51AM +0530, Muni Sekhar wrote: > > > On Thu, Jan 9, 2020 at 1:45 AM Bjorn Helgaas wrote: > > > > On Tue, Jan 07, 2020 at 09:45:13PM +0530, Muni Sekhar wrote: > > > > > Hi, > > > > > > > > > > I have module with Xilinx FPGA. It implements UART(s), SPI(s), > > > > > parallel I/O and interfaces them to the Host CPU via PCI Express bus. > > > > > I see that my system freezes without capturing the crash dump for > > > > > certain tests. I debugged this issue and it was tracked down to the > > > > > below mentioned interrupt handler code. > > > > > > > > > > > > > > > In ISR, first reads the Interrupt Status register using ‘readl()’ as > > > > > given below. > > > > > status = readl(ctrl->reg + INT_STATUS); > > > > > > > > > > > > > > > And then clears the pending interrupts using ‘writel()’ as given blow. > > > > > writel(status, ctrl->reg + INT_STATUS); > > > > > > > > > > > > > > > I've noticed a kernel hang if INT_STATUS register read again after > > > > > clearing the pending interrupts. > > > > > > > > > > Can someone clarify me why the kernel hangs without crash dump incase > > > > > if I read the INT_STATUS register using readl() after clearing the > > > > > pending bits? > > > > > > > > > > Can readl() block? > > > > > > > > readl() should not block in software. Obviously at the hardware CPU > > > > instruction level, the read instruction has to wait for the result of > > > > the read. Since that data is provided by the device, i.e., your FPGA, > > > > it's possible there's a problem there. > > > > > > Thank you very much for your reply. > > > Where can I find the details about what is protocol for reading the > > > ‘memory mapped IO’? Can you point me to any useful links.. > > > I tried locate the exact point of the kernel code where CPU waits for > > > read instruction as given below. > > > readl() -> __raw_readl() -> return *(const volatile u32 __force *)add > > > Do I need to check for the assembly instructions, here? > > > > The C pointer dereference, e.g., "*address", will be some sort of a > > "load" instruction in assembly. The CPU wait isn't explicit; it's > > just that when you load a value, the CPU waits for the value. > > > > > > Can you tell whether the FPGA has received the Memory Read for > > > > INT_STATUS and sent the completion? > I have not seen any ‘missing’ completions on the logic analyser. Is > there any other ways to debug this one? If you see the Memory Read and the associated Completion, and you still see a hang in the kernel, then mostly likely the problem is not in PCIe. I would start by trying to prove that the instruction after the readl() is or is not executed. Bjorn