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From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: Hans de Goede <hdegoede@redhat.com>,
	vipul kumar <vipulk0511@gmail.com>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	linux-kernel@vger.kernel.org, Stable <stable@vger.kernel.org>,
	Srikanth Krishnakar <Srikanth_Krishnakar@mentor.com>,
	Cedric Hombourger <Cedric_Hombourger@mentor.com>,
	x86@kernel.org, Len Brown <len.brown@intel.com>,
	Vipul Kumar <vipul_kumar@mentor.com>
Subject: Re: [v3] x86/tsc: Unset TSC_KNOWN_FREQ and TSC_RELIABLE flags on Intel Bay Trail SoC
Date: Wed, 29 Jan 2020 18:02:53 +0200	[thread overview]
Message-ID: <20200129160253.GK32742@smile.fi.intel.com> (raw)
In-Reply-To: <20200129155910.GJ32742@smile.fi.intel.com>

On Wed, Jan 29, 2020 at 05:59:10PM +0200, Andy Shevchenko wrote:
> On Wed, Jan 29, 2020 at 05:53:53PM +0200, Andy Shevchenko wrote:
> > On Wed, Jan 29, 2020 at 04:13:39PM +0100, Thomas Gleixner wrote:
> > > Hans de Goede <hdegoede@redhat.com> writes:
> > > > On 29-01-2020 15:14, Andy Shevchenko wrote:
> > > >>> The only one which is possibly suspicious here is this line:
> > > >>>
> > > >>>   * 0111:   25 * 32 /  9  =  88.8889 MHz
> > > >>>
> > > >>> The SDM says 88.9 MHz for this one.
> > > 
> > > I trust math more than the SDM :)
> > > 
> > > >> Anyway it seems need to be fixed as well.
> > > >> 
> > > >> Btw, why we are mentioning 20 / 6 and 28 / 6 when arithmetically
> > > >> it's the same as 10 / 3 and 14 / 3?
> > > >
> > > > I copied the BYT values from Thomas' email and I guess he did not
> > > > get around to simplifying them, I'll use the simplified versions
> > > > for my patch.
> > > 
> > > Too tired, too lazy :)
> > > 
> > > Andy, can you please make sure that people inside Intel who can look
> > > into the secrit documentation confirm what we are aiming for?
> > > 
> > > Ideally they should provide the X-tal frequency and the mult/div pair
> > > themself :)
> > 
> > So, I don't have access to the CPU core documentation (and may be will not be
> > given), nevertheless I dug a bit to what I have for Cherrytrail. So, the XTAL
> > is 19.2MHz, which becomes 100MHz and 1600MHz by some root PLL, then, the latter
> > two frequencies are being used by another PLL to provide a reference clock (*)
> > to PLL which derives CPU clock.
> 
> > *) According to colleagues of mine it's a fixed rate source.
> 
> One more thing.
> 
> Depends on SKU it may be 400MHz, 320MHz, 200MHz or 333MHz.

Aha, found better precision for the last one, 333.33MHz.

> (I guess these values should be kinda references in the table)
> 
> > That's all what I have.

-- 
With Best Regards,
Andy Shevchenko



  reply	other threads:[~2020-01-29 16:02 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-21 14:41 [v3] x86/tsc: Unset TSC_KNOWN_FREQ and TSC_RELIABLE flags on Intel Bay Trail SoC Vipul Kumar
2020-01-21 15:24 ` Andy Shevchenko
2020-01-21 17:45 ` Thomas Gleixner
     [not found]   ` <CADdC98RJpsvu_zWehNGDDN=W11rD11NSPaodg-zuaXsHuOJYTQ@mail.gmail.com>
2020-01-22 14:45     ` Thomas Gleixner
     [not found]       ` <CADdC98TE4oNWZyEsqXzr+zJtfdTTOyeeuHqu1u04X_ktLHo-Hg@mail.gmail.com>
2020-01-23 14:12         ` Thomas Gleixner
2020-01-23 14:41         ` Andy Shevchenko
2020-01-23 21:18           ` Hans de Goede
2020-01-24  8:35             ` Thomas Gleixner
2020-01-24  9:11               ` Hans de Goede
2020-01-24 11:55                 ` Thomas Gleixner
2020-01-24 15:54                   ` Hans de Goede
     [not found]                     ` <CADdC98To8VKOUWnR+8zAJ04vgdc4vJoh2h96588+5XFer9YTJw@mail.gmail.com>
2020-01-28 14:23                       ` Hans de Goede
2020-01-28 14:39                         ` vipul kumar
2020-01-28 15:11                       ` Thomas Gleixner
2020-01-28 18:57                   ` Hans de Goede
2020-01-28 22:39                     ` Thomas Gleixner
2020-01-29 13:03                       ` Andy Shevchenko
2020-01-29 13:21                         ` Hans de Goede
2020-01-29 14:14                           ` Andy Shevchenko
2020-01-29 14:27                             ` Hans de Goede
2020-01-29 15:13                               ` Thomas Gleixner
2020-01-29 15:53                                 ` Andy Shevchenko
2020-01-29 15:59                                   ` Andy Shevchenko
2020-01-29 16:02                                     ` Andy Shevchenko [this message]
2020-01-29 20:57                                   ` Thomas Gleixner
2020-01-30  8:54                                     ` Hans de Goede
2020-02-13 18:32                                     ` Dave Hansen
2020-02-13 21:06                                       ` Thomas Gleixner
2020-01-29 15:14                               ` David Laight
2020-01-29 11:43             ` vipul kumar
2020-01-29  5:20       ` vipul kumar
     [not found] ` <20200122022619.B95C024655@mail.kernel.org>
2020-01-22  4:24   ` Kumar, Vipul

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