From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 60E97C2D0B1 for ; Tue, 4 Feb 2020 13:47:53 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2835B20730 for ; Tue, 4 Feb 2020 13:47:53 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2835B20730 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B7F006EF27; Tue, 4 Feb 2020 13:47:52 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 51D7C6EF27 for ; Tue, 4 Feb 2020 13:47:51 +0000 (UTC) X-Amp-Result: UNSCANNABLE X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 04 Feb 2020 05:47:45 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,401,1574150400"; d="scan'208";a="219753576" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by orsmga007.jf.intel.com with SMTP; 04 Feb 2020 05:47:42 -0800 Received: by stinkbox (sSMTP sendmail emulation); Tue, 04 Feb 2020 15:47:41 +0200 Date: Tue, 4 Feb 2020 15:47:41 +0200 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: "Souza, Jose" Message-ID: <20200204134741.GK13686@intel.com> References: <20200128235241.169694-1-jose.souza@intel.com> <20200128235241.169694-2-jose.souza@intel.com> <20200129114257.GR13686@intel.com> <3ab6b8071f4af31d0c6059748c6b5c54bfabd587.camel@intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <3ab6b8071f4af31d0c6059748c6b5c54bfabd587.camel@intel.com> X-Patchwork-Hint: comment User-Agent: Mutt/1.10.1 (2018-07-13) Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915/dgfx: Do not write in removed FBC fence registers X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "intel-gfx@lists.freedesktop.org" , "De Marchi, Lucas" , "Pandiyan, Dhinakaran" Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Tue, Feb 04, 2020 at 02:06:23AM +0000, Souza, Jose wrote: > On Wed, 2020-01-29 at 13:42 +0200, Ville Syrj=E4l=E4 wrote: > > On Tue, Jan 28, 2020 at 03:52:41PM -0800, Jos=E9 Roberto de Souza > > wrote: > > > From: Radhakrishna Sripada > > > = > > > dgfx platforms do not support CPU fence and FBC host tracking so > > > lets avoid write to removed registers. > > > = > > > Cc: Rodrigo Vivi > > > Cc: Matt Roper > > > Cc: Dhinakaran Pandiyan > > > Signed-off-by: Radhakrishna Sripada > > > > > > Signed-off-by: Lucas De Marchi > > > Signed-off-by: Jos=E9 Roberto de Souza > > > --- > > > drivers/gpu/drm/i915/display/intel_fbc.c | 7 ++++++- > > > 1 file changed, 6 insertions(+), 1 deletion(-) > > > = > > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c > > > b/drivers/gpu/drm/i915/display/intel_fbc.c > > > index 1f0d24a1dec1..12900b8ce28e 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c > > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c > > > @@ -314,7 +314,12 @@ static void gen7_fbc_activate(struct > > > drm_i915_private *dev_priv) > > > break; > > > } > > > = > > > - if (params->fence_id >=3D 0) { > > > + if (IS_DGFX(dev_priv)) { > > > + /* > > > + * dGFX GPUs don't have apperture or fences and only > > > rely on FBC > > > + * render nuke to track frontbuffer modifications > > > + */ > > > + } else if (params->fence_id >=3D 0) { > > > dpfc_ctl |=3D IVB_DPFC_CTL_FENCE_EN; > > > intel_de_write(dev_priv, SNB_DPFC_CTL_SA, > > > SNB_CPU_FENCE_ENABLE | params- > > > >fence_id); > > = > > if (fence) { > > do stuff > > } else if (num_fences) { > > do other stuff > > } > = > Did not get what you want here. Don't add a silly looking empty if block. And don't make the assumption that dgfx is the only thing that has no fences, instead actually check if we have fences or not. > It is covering all cases: > - DGFX that don't have the registers > - Setting the registers when fence_id >=3D 0 > - Clearing the register when fences_id =3D=3D -1 > = > > = > > > -- = > > > 2.25.0 > > > = > > > _______________________________________________ > > > Intel-gfx mailing list > > > Intel-gfx@lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx