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[209.132.180.67]) by mx.google.com with ESMTP id j70si339688oib.219.2020.02.05.08.43.34; Wed, 05 Feb 2020 08:43:34 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of kvm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of kvm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=kvm-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727052AbgBEQnc (ORCPT + 5 others); Wed, 5 Feb 2020 11:43:32 -0500 Received: from lhrrgout.huawei.com ([185.176.76.210]:2382 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726359AbgBEQnc (ORCPT ); Wed, 5 Feb 2020 11:43:32 -0500 Received: from lhreml703-cah.china.huawei.com (unknown [172.18.7.106]) by Forcepoint Email with ESMTP id 2BCBD87DFEB78505D9D6; Wed, 5 Feb 2020 16:43:30 +0000 (GMT) Received: from lhreml710-chm.china.huawei.com (10.201.108.61) by lhreml703-cah.china.huawei.com (10.201.108.44) with Microsoft SMTP Server (TLS) id 14.3.408.0; Wed, 5 Feb 2020 16:43:29 +0000 Received: from localhost (10.202.226.57) by lhreml710-chm.china.huawei.com (10.201.108.61) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 5 Feb 2020 16:43:29 +0000 Date: Wed, 5 Feb 2020 16:43:28 +0000 From: Jonathan Cameron To: Dongjiu Geng CC: , , , , , , , , , , , , , , , Subject: Re: [PATCH v22 4/9] ACPI: Build Hardware Error Source Table Message-ID: <20200205164328.00006f1e@Huawei.com> In-Reply-To: <1578483143-14905-5-git-send-email-gengdongjiu@huawei.com> References: <1578483143-14905-1-git-send-email-gengdongjiu@huawei.com> <1578483143-14905-5-git-send-email-gengdongjiu@huawei.com> Organization: Huawei Technologies Research and Development (UK) Ltd. X-Mailer: Claws Mail 3.17.4 (GTK+ 2.24.32; i686-w64-mingw32) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.202.226.57] X-ClientProxiedBy: lhreml712-chm.china.huawei.com (10.201.108.63) To lhreml710-chm.china.huawei.com (10.201.108.61) X-CFilter-Loop: Reflected Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-TUID: D3QLsOttYVaM On Wed, 8 Jan 2020 19:32:18 +0800 Dongjiu Geng wrote: > This patch builds Hardware Error Source Table(HEST) via fw_cfg blobs. > Now it only supports ARMv8 SEA, a type of Generic Hardware Error > Source version 2(GHESv2) error source. Afterwards, we can extend > the supported types if needed. For the CPER section, currently it > is memory section because kernel mainly wants userspace to handle > the memory errors. > > This patch follows the spec ACPI 6.2 to build the Hardware Error > Source table. For more detailed information, please refer to > document: docs/specs/acpi_hest_ghes.rst > > build_append_ghes_notify() will help to add Hardware Error Notification > to ACPI tables without using packed C structures and avoid endianness > issues as API doesn't need explicit conversion. > > Signed-off-by: Dongjiu Geng > Signed-off-by: Xiang Zheng > Reviewed-by: Michael S. Tsirkin > Acked-by: Xiang Zheng Hi. I was forwards porting my old series adding CCIX error injection support and came across a place this could 'possibly' be improved. I say possibly because it's really about enabling more flexibility in how this code is reused than actually 'fixing' anything here. If you don't make the change here, I'll just add a precursor patch to my series. Just seems nice to tidy it up at source. The rest of the parts of this series I am using seems to work great. Thanks! Jonathan > --- > hw/acpi/ghes.c | 118 ++++++++++++++++++++++++++++++++++++++++++++++- > hw/arm/virt-acpi-build.c | 2 + > include/hw/acpi/ghes.h | 40 ++++++++++++++++ > 3 files changed, 159 insertions(+), 1 deletion(-) > > diff --git a/hw/acpi/ghes.c b/hw/acpi/ghes.c > index b7fdbbb..9d37798 100644 > --- a/hw/acpi/ghes.c > +++ b/hw/acpi/ghes.c > @@ -34,9 +34,42 @@ > + ... > +/* Build Generic Hardware Error Source version 2 (GHESv2) */ > +static void build_ghes_v2(GArray *table_data, int source_id, BIOSLinker *linker) This function takes source ID, which uses the enum of all sources registered. However, it doesn't use it to locate the actual physical addresses. Currently the code effectively assumes the value is 0. > +{ > + uint64_t address_offset; > + /* > + * Type: > + * Generic Hardware Error Source version 2(GHESv2 - Type 10) > + */ > + build_append_int_noprefix(table_data, ACPI_GHES_SOURCE_GENERIC_ERROR_V2, 2); > + /* Source Id */ > + build_append_int_noprefix(table_data, source_id, 2); > + /* Related Source Id */ > + build_append_int_noprefix(table_data, 0xffff, 2); > + /* Flags */ > + build_append_int_noprefix(table_data, 0, 1); > + /* Enabled */ > + build_append_int_noprefix(table_data, 1, 1); > + > + /* Number of Records To Pre-allocate */ > + build_append_int_noprefix(table_data, 1, 4); > + /* Max Sections Per Record */ > + build_append_int_noprefix(table_data, 1, 4); > + /* Max Raw Data Length */ > + build_append_int_noprefix(table_data, ACPI_GHES_MAX_RAW_DATA_LENGTH, 4); > + > + address_offset = table_data->len; > + /* Error Status Address */ > + build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 0x40, 0, > + 4 /* QWord access */, 0); > + bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, > + address_offset + GAS_ADDR_OFFSET, > + sizeof(uint64_t), ACPI_GHES_ERRORS_FW_CFG_FILE, 0); The offset here would need to be source_id * sizeof(uint64_t) I think > + > + /* > + * Notification Structure > + * Now only enable ARMv8 SEA notification type > + */ > + build_ghes_hw_error_notification(table_data, ACPI_GHES_NOTIFY_SEA); Perhaps a switch for this to allow for other options later. switch (source_id) { case ACPI_HEST_SRC_ID_SEA: ... break; default: //print some error message. } > + > + /* Error Status Block Length */ > + build_append_int_noprefix(table_data, ACPI_GHES_MAX_RAW_DATA_LENGTH, 4); > + > + /* > + * Read Ack Register > + * ACPI 6.1: 18.3.2.8 Generic Hardware Error Source > + * version 2 (GHESv2 - Type 10) > + */ > + address_offset = table_data->len; > + build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 0x40, 0, > + 4 /* QWord access */, 0); > + bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, > + address_offset + GAS_ADDR_OFFSET, > + sizeof(uint64_t), ACPI_GHES_ERRORS_FW_CFG_FILE, > + ACPI_GHES_ERROR_SOURCE_COUNT * sizeof(uint64_t)); Offset of (ACPI_GHES_ERROR_SOURCE_COUNT + source_id) * sizeof(uint64_t) > + > + /* > + * Read Ack Preserve > + * We only provide the first bit in Read Ack Register to OSPM to write > + * while the other bits are preserved. > + */ > + build_append_int_noprefix(table_data, ~0x1ULL, 8); > + /* Read Ack Write */ > + build_append_int_noprefix(table_data, 0x1, 8); > +} From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8EA51C35247 for ; Wed, 5 Feb 2020 16:44:48 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 65DDA217F4 for ; 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Wed, 05 Feb 2020 11:43:41 -0500 Received: from lhreml703-cah.china.huawei.com (unknown [172.18.7.106]) by Forcepoint Email with ESMTP id 2BCBD87DFEB78505D9D6; Wed, 5 Feb 2020 16:43:30 +0000 (GMT) Received: from lhreml710-chm.china.huawei.com (10.201.108.61) by lhreml703-cah.china.huawei.com (10.201.108.44) with Microsoft SMTP Server (TLS) id 14.3.408.0; Wed, 5 Feb 2020 16:43:29 +0000 Received: from localhost (10.202.226.57) by lhreml710-chm.china.huawei.com (10.201.108.61) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 5 Feb 2020 16:43:29 +0000 Date: Wed, 5 Feb 2020 16:43:28 +0000 From: Jonathan Cameron To: Dongjiu Geng Subject: Re: [PATCH v22 4/9] ACPI: Build Hardware Error Source Table Message-ID: <20200205164328.00006f1e@Huawei.com> In-Reply-To: <1578483143-14905-5-git-send-email-gengdongjiu@huawei.com> References: <1578483143-14905-1-git-send-email-gengdongjiu@huawei.com> <1578483143-14905-5-git-send-email-gengdongjiu@huawei.com> Organization: Huawei Technologies Research and Development (UK) Ltd. X-Mailer: Claws Mail 3.17.4 (GTK+ 2.24.32; i686-w64-mingw32) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.202.226.57] X-ClientProxiedBy: lhreml712-chm.china.huawei.com (10.201.108.63) To lhreml710-chm.china.huawei.com (10.201.108.61) X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 185.176.76.210 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: fam@euphon.net, peter.maydell@linaro.org, ehabkost@redhat.com, kvm@vger.kernel.org, mst@redhat.com, mtosatti@redhat.com, qemu-devel@nongnu.org, linuxarm@huawei.com, shannon.zhaosl@gmail.com, zhengxiang9@huawei.com, qemu-arm@nongnu.org, james.morse@arm.com, xuwei5@huawei.com, imammedo@redhat.com, pbonzini@redhat.com, rth@twiddle.net Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Wed, 8 Jan 2020 19:32:18 +0800 Dongjiu Geng wrote: > This patch builds Hardware Error Source Table(HEST) via fw_cfg blobs. > Now it only supports ARMv8 SEA, a type of Generic Hardware Error > Source version 2(GHESv2) error source. Afterwards, we can extend > the supported types if needed. For the CPER section, currently it > is memory section because kernel mainly wants userspace to handle > the memory errors. > > This patch follows the spec ACPI 6.2 to build the Hardware Error > Source table. For more detailed information, please refer to > document: docs/specs/acpi_hest_ghes.rst > > build_append_ghes_notify() will help to add Hardware Error Notification > to ACPI tables without using packed C structures and avoid endianness > issues as API doesn't need explicit conversion. > > Signed-off-by: Dongjiu Geng > Signed-off-by: Xiang Zheng > Reviewed-by: Michael S. Tsirkin > Acked-by: Xiang Zheng Hi. I was forwards porting my old series adding CCIX error injection support and came across a place this could 'possibly' be improved. I say possibly because it's really about enabling more flexibility in how this code is reused than actually 'fixing' anything here. If you don't make the change here, I'll just add a precursor patch to my series. Just seems nice to tidy it up at source. The rest of the parts of this series I am using seems to work great. Thanks! Jonathan > --- > hw/acpi/ghes.c | 118 ++++++++++++++++++++++++++++++++++++++++++++++- > hw/arm/virt-acpi-build.c | 2 + > include/hw/acpi/ghes.h | 40 ++++++++++++++++ > 3 files changed, 159 insertions(+), 1 deletion(-) > > diff --git a/hw/acpi/ghes.c b/hw/acpi/ghes.c > index b7fdbbb..9d37798 100644 > --- a/hw/acpi/ghes.c > +++ b/hw/acpi/ghes.c > @@ -34,9 +34,42 @@ > + ... > +/* Build Generic Hardware Error Source version 2 (GHESv2) */ > +static void build_ghes_v2(GArray *table_data, int source_id, BIOSLinker *linker) This function takes source ID, which uses the enum of all sources registered. However, it doesn't use it to locate the actual physical addresses. Currently the code effectively assumes the value is 0. > +{ > + uint64_t address_offset; > + /* > + * Type: > + * Generic Hardware Error Source version 2(GHESv2 - Type 10) > + */ > + build_append_int_noprefix(table_data, ACPI_GHES_SOURCE_GENERIC_ERROR_V2, 2); > + /* Source Id */ > + build_append_int_noprefix(table_data, source_id, 2); > + /* Related Source Id */ > + build_append_int_noprefix(table_data, 0xffff, 2); > + /* Flags */ > + build_append_int_noprefix(table_data, 0, 1); > + /* Enabled */ > + build_append_int_noprefix(table_data, 1, 1); > + > + /* Number of Records To Pre-allocate */ > + build_append_int_noprefix(table_data, 1, 4); > + /* Max Sections Per Record */ > + build_append_int_noprefix(table_data, 1, 4); > + /* Max Raw Data Length */ > + build_append_int_noprefix(table_data, ACPI_GHES_MAX_RAW_DATA_LENGTH, 4); > + > + address_offset = table_data->len; > + /* Error Status Address */ > + build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 0x40, 0, > + 4 /* QWord access */, 0); > + bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, > + address_offset + GAS_ADDR_OFFSET, > + sizeof(uint64_t), ACPI_GHES_ERRORS_FW_CFG_FILE, 0); The offset here would need to be source_id * sizeof(uint64_t) I think > + > + /* > + * Notification Structure > + * Now only enable ARMv8 SEA notification type > + */ > + build_ghes_hw_error_notification(table_data, ACPI_GHES_NOTIFY_SEA); Perhaps a switch for this to allow for other options later. switch (source_id) { case ACPI_HEST_SRC_ID_SEA: ... break; default: //print some error message. } > + > + /* Error Status Block Length */ > + build_append_int_noprefix(table_data, ACPI_GHES_MAX_RAW_DATA_LENGTH, 4); > + > + /* > + * Read Ack Register > + * ACPI 6.1: 18.3.2.8 Generic Hardware Error Source > + * version 2 (GHESv2 - Type 10) > + */ > + address_offset = table_data->len; > + build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 0x40, 0, > + 4 /* QWord access */, 0); > + bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, > + address_offset + GAS_ADDR_OFFSET, > + sizeof(uint64_t), ACPI_GHES_ERRORS_FW_CFG_FILE, > + ACPI_GHES_ERROR_SOURCE_COUNT * sizeof(uint64_t)); Offset of (ACPI_GHES_ERROR_SOURCE_COUNT + source_id) * sizeof(uint64_t) > + > + /* > + * Read Ack Preserve > + * We only provide the first bit in Read Ack Register to OSPM to write > + * while the other bits are preserved. > + */ > + build_append_int_noprefix(table_data, ~0x1ULL, 8); > + /* Read Ack Write */ > + build_append_int_noprefix(table_data, 0x1, 8); > +}