From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andy Shevchenko Subject: Re: Re: [PATCH] spi: pxa2xx: Add CS control clock quirk Date: Thu, 13 Feb 2020 19:18:36 +0200 Message-ID: <20200213171836.GD10400@smile.fi.intel.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Cc: Jarkko Nikula , Rajat Jain , Daniel Mack , Haojian Zhuang , Robert Jarzmik , Mark Brown , "linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" , "linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , Evan Green , "rajatxjain-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org" , "evgreen-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org" , "Muthukrishnan, Porselvan" To: "Srivastava, Shobhit" Return-path: Content-Disposition: inline In-Reply-To: Sender: linux-spi-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-ID: On Thu, Feb 13, 2020 at 04:57:24PM +0000, Srivastava, Shobhit wrote: > > On 2/12/20 12:34 AM, Rajat Jain wrote: ... > > I wonder is it enough to have this quick toggling only or is time or actually > > number of clock cycles dependent? Now there is no delay between but I'm > > thinking if it needs certain number cycles does this still work when using low > > ssp_clk rates similar than in commit d0283eb2dbc1 ("spi: > > pxa2xx: Add output control for multiple Intel LPSS chip selects"). > > > > I'm thinking can this be done only once after resume and may other LPSS > > blocks need the same? I.e. should this be done in drivers/mfd/intel-lpss.c? > This behavior is seen after S0ix resume, but it is not seen after S3 resume. I already commented in the other thread about this. Have you checked what's going on in intel_lpss_suspend() and intel_lpss_resume() for your case? Is intel_lpss_prepare() called during S0ix exit? > I am thinking that it happens because we are not enabling the SSP after resume. > It is deferred until we need to send data. By enabling the SSP in resume, I don’t see the issue. > For S3, I think BIOS re-enables the SSP in resume flow. -- With Best Regards, Andy Shevchenko From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A952C2BA83 for ; Thu, 13 Feb 2020 17:20:57 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3B269206DB for ; Thu, 13 Feb 2020 17:20:57 +0000 (UTC) Authentication-Results: mail.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org T24gVGh1LCBGZWIgMTMsIDIwMjAgYXQgMDQ6NTc6MjRQTSArMDAwMCwgU3JpdmFzdGF2YSwgU2hv YmhpdCB3cm90ZToKPiA+IE9uIDIvMTIvMjAgMTI6MzQgQU0sIFJhamF0IEphaW4gd3JvdGU6Cgou Li4KCj4gPiBJIHdvbmRlciBpcyBpdCBlbm91Z2ggdG8gaGF2ZSB0aGlzIHF1aWNrIHRvZ2dsaW5n IG9ubHkgb3IgaXMgdGltZSBvciBhY3R1YWxseQo+ID4gbnVtYmVyIG9mIGNsb2NrIGN5Y2xlcyBk ZXBlbmRlbnQ/IE5vdyB0aGVyZSBpcyBubyBkZWxheSBiZXR3ZWVuIGJ1dCBJJ20KPiA+IHRoaW5r aW5nIGlmIGl0IG5lZWRzIGNlcnRhaW4gbnVtYmVyIGN5Y2xlcyBkb2VzIHRoaXMgc3RpbGwgd29y ayB3aGVuIHVzaW5nIGxvdwo+ID4gc3NwX2NsayByYXRlcyBzaW1pbGFyIHRoYW4gaW4gY29tbWl0 IGQwMjgzZWIyZGJjMSAoInNwaToKPiA+IHB4YTJ4eDogQWRkIG91dHB1dCBjb250cm9sIGZvciBt dWx0aXBsZSBJbnRlbCBMUFNTIGNoaXAgc2VsZWN0cyIpLgo+ID4gCj4gPiBJJ20gdGhpbmtpbmcg Y2FuIHRoaXMgYmUgZG9uZSBvbmx5IG9uY2UgYWZ0ZXIgcmVzdW1lIGFuZCBtYXkgb3RoZXIgTFBT Uwo+ID4gYmxvY2tzIG5lZWQgdGhlIHNhbWU/IEkuZS4gc2hvdWxkIHRoaXMgYmUgZG9uZSBpbiBk cml2ZXJzL21mZC9pbnRlbC1scHNzLmM/Cgo+IFRoaXMgYmVoYXZpb3IgaXMgc2VlbiBhZnRlciBT MGl4IHJlc3VtZSwgYnV0IGl0IGlzIG5vdCBzZWVuIGFmdGVyIFMzIHJlc3VtZS4KCkkgYWxyZWFk eSBjb21tZW50ZWQgaW4gdGhlIG90aGVyIHRocmVhZCBhYm91dCB0aGlzLgoKSGF2ZSB5b3UgY2hl Y2tlZCB3aGF0J3MgZ29pbmcgb24gaW4gaW50ZWxfbHBzc19zdXNwZW5kKCkgYW5kCmludGVsX2xw c3NfcmVzdW1lKCkgZm9yIHlvdXIgY2FzZT8KCklzIGludGVsX2xwc3NfcHJlcGFyZSgpIGNhbGxl ZCBkdXJpbmcgUzBpeCBleGl0PwoKPiBJIGFtIHRoaW5raW5nIHRoYXQgaXQgaGFwcGVucyBiZWNh dXNlIHdlIGFyZSBub3QgZW5hYmxpbmcgdGhlIFNTUCBhZnRlciByZXN1bWUuIAo+IEl0IGlzIGRl ZmVycmVkIHVudGlsIHdlIG5lZWQgdG8gc2VuZCBkYXRhLiBCeSBlbmFibGluZyB0aGUgU1NQIGlu IHJlc3VtZSwgSSBkb27igJl0IHNlZSB0aGUgaXNzdWUuCj4gRm9yIFMzLCBJIHRoaW5rIEJJT1Mg cmUtZW5hYmxlcyB0aGUgU1NQIGluIHJlc3VtZSBmbG93LgoKLS0gCldpdGggQmVzdCBSZWdhcmRz LApBbmR5IFNoZXZjaGVua28KCgoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX18KbGludXgtYXJtLWtlcm5lbCBtYWlsaW5nIGxpc3QKbGludXgtYXJtLWtlcm5l bEBsaXN0cy5pbmZyYWRlYWQub3JnCmh0dHA6Ly9saXN0cy5pbmZyYWRlYWQub3JnL21haWxtYW4v bGlzdGluZm8vbGludXgtYXJtLWtlcm5lbAo= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0360C2BA83 for ; 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Thu, 13 Feb 2020 19:18:36 +0200 Date: Thu, 13 Feb 2020 19:18:36 +0200 From: Andy Shevchenko To: "Srivastava, Shobhit" Cc: Jarkko Nikula , Rajat Jain , Daniel Mack , Haojian Zhuang , Robert Jarzmik , Mark Brown , "linux-arm-kernel@lists.infradead.org" , "linux-spi@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Evan Green , "rajatxjain@gmail.com" , "evgreen@google.com" , "Muthukrishnan, Porselvan" Subject: Re: Re: [PATCH] spi: pxa2xx: Add CS control clock quirk Message-ID: <20200213171836.GD10400@smile.fi.intel.com> References: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Feb 13, 2020 at 04:57:24PM +0000, Srivastava, Shobhit wrote: > > On 2/12/20 12:34 AM, Rajat Jain wrote: ... > > I wonder is it enough to have this quick toggling only or is time or actually > > number of clock cycles dependent? Now there is no delay between but I'm > > thinking if it needs certain number cycles does this still work when using low > > ssp_clk rates similar than in commit d0283eb2dbc1 ("spi: > > pxa2xx: Add output control for multiple Intel LPSS chip selects"). > > > > I'm thinking can this be done only once after resume and may other LPSS > > blocks need the same? I.e. should this be done in drivers/mfd/intel-lpss.c? > This behavior is seen after S0ix resume, but it is not seen after S3 resume. I already commented in the other thread about this. Have you checked what's going on in intel_lpss_suspend() and intel_lpss_resume() for your case? Is intel_lpss_prepare() called during S0ix exit? > I am thinking that it happens because we are not enabling the SSP after resume. > It is deferred until we need to send data. By enabling the SSP in resume, I don’t see the issue. > For S3, I think BIOS re-enables the SSP in resume flow. -- With Best Regards, Andy Shevchenko