From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] drm/i915/gt: Ensure 'ENABLE_BOOT_FETCH' is enabled before ppGTT
Date: Thu, 13 Feb 2020 19:57:56 +0200 [thread overview]
Message-ID: <20200213175756.GH13686@intel.com> (raw)
In-Reply-To: <20200213154759.3641671-1-chris@chris-wilson.co.uk>
On Thu, Feb 13, 2020 at 03:47:59PM +0000, Chris Wilson wrote:
> Cryptic notes in bspec say that "The MBC Driver Boot Enable bit in MBCTL
> register must be set before this register is written to upon boot up
> (including S3 exit)."
>
> We tried adding it to our list of verified workarounds, but our
> self checks spot that the bit does not stick. It's only meant to be
> cleared after a FLR. As it fails our verification, just blindly apply
> the bit prior to loading the ppGTT.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_ring_submission.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> index f70b903a98bc..e41a329d435a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> @@ -642,6 +642,9 @@ static void set_pp_dir(struct intel_engine_cs *engine)
> if (vm) {
> struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
>
> + intel_uncore_rmw(engine->uncore, GEN6_MBCTL,
> + 0, GEN6_MBCTL_ENABLE_BOOT_FETCH)
Wasn't setting this bit implicated in some regressions long ago?
> +
> ENGINE_WRITE(engine, RING_PP_DIR_DCLV, PP_DIR_DCLV_2G);
> ENGINE_WRITE(engine, RING_PP_DIR_BASE,
> px_base(ppgtt->pd)->ggtt_offset << 10);
> --
> 2.25.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-02-13 17:58 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-13 15:47 [Intel-gfx] [PATCH] drm/i915/gt: Ensure 'ENABLE_BOOT_FETCH' is enabled before ppGTT Chris Wilson
2020-02-13 17:38 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for " Patchwork
2020-02-13 17:57 ` Ville Syrjälä [this message]
2020-02-13 18:07 ` [Intel-gfx] [PATCH] " Chris Wilson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200213175756.GH13686@intel.com \
--to=ville.syrjala@linux.intel.com \
--cc=chris@chris-wilson.co.uk \
--cc=intel-gfx@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.