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Thu, 13 Feb 2020 12:19:32 -0800 (PST) From: Andrey Lebedev To: mripard@kernel.org, wens@csie.org, airlied@linux.ie, daniel@ffwll.ch, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/3] drm/sun4i: tcon: Introduce LVDS setup routine setting Date: Thu, 13 Feb 2020 22:18:53 +0200 Message-Id: <20200213201854.810-1-andrey.lebedev@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200210195633.GA21832@kedthinkpad> References: <20200210195633.GA21832@kedthinkpad> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200213_121935_039532_BCED8B3F X-CRM114-Status: GOOD ( 15.17 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrey Lebedev , linux-sunxi@googlegroups.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Andrey Lebedev Different sunxi flavors require slightly different sequence for enabling LVDS output. This allows to differentiate between them. Signed-off-by: Andrey Lebedev --- drivers/gpu/drm/sun4i/sun4i_tcon.c | 68 ++++++++++++++++-------------- drivers/gpu/drm/sun4i/sun4i_tcon.h | 3 ++ 2 files changed, 39 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c index c81cdce6ed55..cc6b05ca2c69 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c @@ -114,46 +114,48 @@ static void sun4i_tcon_channel_set_status(struct sun4i_tcon *tcon, int channel, } } +static void sun6i_tcon_setup_lvds_phy(struct sun4i_tcon *tcon, + const struct drm_encoder *encoder) +{ + u8 val; + + regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, + SUN6I_TCON0_LVDS_ANA0_C(2) | + SUN6I_TCON0_LVDS_ANA0_V(3) | + SUN6I_TCON0_LVDS_ANA0_PD(2) | + SUN6I_TCON0_LVDS_ANA0_EN_LDO); + udelay(2); + + regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, + SUN6I_TCON0_LVDS_ANA0_EN_MB, + SUN6I_TCON0_LVDS_ANA0_EN_MB); + udelay(2); + + regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, + SUN6I_TCON0_LVDS_ANA0_EN_DRVC, + SUN6I_TCON0_LVDS_ANA0_EN_DRVC); + + if (sun4i_tcon_get_pixel_depth(encoder) == 18) + val = 7; + else + val = 0xf; + + regmap_write_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, + SUN6I_TCON0_LVDS_ANA0_EN_DRVD(0xf), + SUN6I_TCON0_LVDS_ANA0_EN_DRVD(val)); + +} + static void sun4i_tcon_lvds_set_status(struct sun4i_tcon *tcon, const struct drm_encoder *encoder, bool enabled) { if (enabled) { - u8 val; - regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, SUN4I_TCON0_LVDS_IF_EN, SUN4I_TCON0_LVDS_IF_EN); - - /* - * As their name suggest, these values only apply to the A31 - * and later SoCs. We'll have to rework this when merging - * support for the older SoCs. - */ - regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, - SUN6I_TCON0_LVDS_ANA0_C(2) | - SUN6I_TCON0_LVDS_ANA0_V(3) | - SUN6I_TCON0_LVDS_ANA0_PD(2) | - SUN6I_TCON0_LVDS_ANA0_EN_LDO); - udelay(2); - - regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, - SUN6I_TCON0_LVDS_ANA0_EN_MB, - SUN6I_TCON0_LVDS_ANA0_EN_MB); - udelay(2); - - regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, - SUN6I_TCON0_LVDS_ANA0_EN_DRVC, - SUN6I_TCON0_LVDS_ANA0_EN_DRVC); - - if (sun4i_tcon_get_pixel_depth(encoder) == 18) - val = 7; - else - val = 0xf; - - regmap_write_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, - SUN6I_TCON0_LVDS_ANA0_EN_DRVD(0xf), - SUN6I_TCON0_LVDS_ANA0_EN_DRVD(val)); + if (tcon->quirks->setup_lvds_phy) + tcon->quirks->setup_lvds_phy(tcon, encoder); } else { regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, SUN4I_TCON0_LVDS_IF_EN, 0); @@ -1465,12 +1467,14 @@ static const struct sun4i_tcon_quirks sun8i_a33_quirks = { .has_channel_0 = true, .has_lvds_alt = true, .dclk_min_div = 1, + .setup_lvds_phy = sun6i_tcon_setup_lvds_phy, }; static const struct sun4i_tcon_quirks sun8i_a83t_lcd_quirks = { .supports_lvds = true, .has_channel_0 = true, .dclk_min_div = 1, + .setup_lvds_phy = sun6i_tcon_setup_lvds_phy, }; static const struct sun4i_tcon_quirks sun8i_a83t_tv_quirks = { diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h index a62ec826ae71..2974e59ef9f2 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.h +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h @@ -228,6 +228,9 @@ struct sun4i_tcon_quirks { /* callback to handle tcon muxing options */ int (*set_mux)(struct sun4i_tcon *, const struct drm_encoder *); + /* handler for LVDS setup routine */ + void (*setup_lvds_phy)(struct sun4i_tcon *tcon, + const struct drm_encoder *encoder); }; struct sun4i_tcon { -- 2.20.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.3 required=3.0 tests=DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F81FC3B18F for ; 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Thu, 13 Feb 2020 12:19:32 -0800 (PST) Received: from localhost.localdomain ([5.20.204.163]) by smtp.gmail.com with ESMTPSA id s22sm2209470ljm.41.2020.02.13.12.19.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Feb 2020 12:19:32 -0800 (PST) From: Andrey Lebedev To: mripard@kernel.org, wens@csie.org, airlied@linux.ie, daniel@ffwll.ch, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/3] drm/sun4i: tcon: Introduce LVDS setup routine setting Date: Thu, 13 Feb 2020 22:18:53 +0200 Message-Id: <20200213201854.810-1-andrey.lebedev@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200210195633.GA21832@kedthinkpad> References: <20200210195633.GA21832@kedthinkpad> MIME-Version: 1.0 X-Mailman-Approved-At: Fri, 14 Feb 2020 08:07:58 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrey Lebedev , linux-sunxi@googlegroups.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Andrey Lebedev Different sunxi flavors require slightly different sequence for enabling LVDS output. This allows to differentiate between them. Signed-off-by: Andrey Lebedev --- drivers/gpu/drm/sun4i/sun4i_tcon.c | 68 ++++++++++++++++-------------- drivers/gpu/drm/sun4i/sun4i_tcon.h | 3 ++ 2 files changed, 39 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c index c81cdce6ed55..cc6b05ca2c69 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c @@ -114,46 +114,48 @@ static void sun4i_tcon_channel_set_status(struct sun4i_tcon *tcon, int channel, } } +static void sun6i_tcon_setup_lvds_phy(struct sun4i_tcon *tcon, + const struct drm_encoder *encoder) +{ + u8 val; + + regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, + SUN6I_TCON0_LVDS_ANA0_C(2) | + SUN6I_TCON0_LVDS_ANA0_V(3) | + SUN6I_TCON0_LVDS_ANA0_PD(2) | + SUN6I_TCON0_LVDS_ANA0_EN_LDO); + udelay(2); + + regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, + SUN6I_TCON0_LVDS_ANA0_EN_MB, + SUN6I_TCON0_LVDS_ANA0_EN_MB); + udelay(2); + + regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, + SUN6I_TCON0_LVDS_ANA0_EN_DRVC, + SUN6I_TCON0_LVDS_ANA0_EN_DRVC); + + if (sun4i_tcon_get_pixel_depth(encoder) == 18) + val = 7; + else + val = 0xf; + + regmap_write_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, + SUN6I_TCON0_LVDS_ANA0_EN_DRVD(0xf), + SUN6I_TCON0_LVDS_ANA0_EN_DRVD(val)); + +} + static void sun4i_tcon_lvds_set_status(struct sun4i_tcon *tcon, const struct drm_encoder *encoder, bool enabled) { if (enabled) { - u8 val; - regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, SUN4I_TCON0_LVDS_IF_EN, SUN4I_TCON0_LVDS_IF_EN); - - /* - * As their name suggest, these values only apply to the A31 - * and later SoCs. We'll have to rework this when merging - * support for the older SoCs. - */ - regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, - SUN6I_TCON0_LVDS_ANA0_C(2) | - SUN6I_TCON0_LVDS_ANA0_V(3) | - SUN6I_TCON0_LVDS_ANA0_PD(2) | - SUN6I_TCON0_LVDS_ANA0_EN_LDO); - udelay(2); - - regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, - SUN6I_TCON0_LVDS_ANA0_EN_MB, - SUN6I_TCON0_LVDS_ANA0_EN_MB); - udelay(2); - - regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, - SUN6I_TCON0_LVDS_ANA0_EN_DRVC, - SUN6I_TCON0_LVDS_ANA0_EN_DRVC); - - if (sun4i_tcon_get_pixel_depth(encoder) == 18) - val = 7; - else - val = 0xf; - - regmap_write_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, - SUN6I_TCON0_LVDS_ANA0_EN_DRVD(0xf), - SUN6I_TCON0_LVDS_ANA0_EN_DRVD(val)); + if (tcon->quirks->setup_lvds_phy) + tcon->quirks->setup_lvds_phy(tcon, encoder); } else { regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, SUN4I_TCON0_LVDS_IF_EN, 0); @@ -1465,12 +1467,14 @@ static const struct sun4i_tcon_quirks sun8i_a33_quirks = { .has_channel_0 = true, .has_lvds_alt = true, .dclk_min_div = 1, + .setup_lvds_phy = sun6i_tcon_setup_lvds_phy, }; static const struct sun4i_tcon_quirks sun8i_a83t_lcd_quirks = { .supports_lvds = true, .has_channel_0 = true, .dclk_min_div = 1, + .setup_lvds_phy = sun6i_tcon_setup_lvds_phy, }; static const struct sun4i_tcon_quirks sun8i_a83t_tv_quirks = { diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h index a62ec826ae71..2974e59ef9f2 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.h +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h @@ -228,6 +228,9 @@ struct sun4i_tcon_quirks { /* callback to handle tcon muxing options */ int (*set_mux)(struct sun4i_tcon *, const struct drm_encoder *); + /* handler for LVDS setup routine */ + void (*setup_lvds_phy)(struct sun4i_tcon *tcon, + const struct drm_encoder *encoder); }; struct sun4i_tcon { -- 2.20.1 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9DB3C352A3 for ; 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Thu, 13 Feb 2020 12:19:32 -0800 (PST) Received: from localhost.localdomain ([5.20.204.163]) by smtp.gmail.com with ESMTPSA id s22sm2209470ljm.41.2020.02.13.12.19.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Feb 2020 12:19:32 -0800 (PST) From: Andrey Lebedev To: mripard@kernel.org, wens@csie.org, airlied@linux.ie, daniel@ffwll.ch, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: linux-sunxi@googlegroups.com, Andrey Lebedev Subject: [PATCH v3 1/3] drm/sun4i: tcon: Introduce LVDS setup routine setting Date: Thu, 13 Feb 2020 22:18:53 +0200 Message-Id: <20200213201854.810-1-andrey.lebedev@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200210195633.GA21832@kedthinkpad> References: <20200210195633.GA21832@kedthinkpad> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Andrey Lebedev Different sunxi flavors require slightly different sequence for enabling LVDS output. This allows to differentiate between them. Signed-off-by: Andrey Lebedev --- drivers/gpu/drm/sun4i/sun4i_tcon.c | 68 ++++++++++++++++-------------- drivers/gpu/drm/sun4i/sun4i_tcon.h | 3 ++ 2 files changed, 39 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c index c81cdce6ed55..cc6b05ca2c69 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c @@ -114,46 +114,48 @@ static void sun4i_tcon_channel_set_status(struct sun4i_tcon *tcon, int channel, } } +static void sun6i_tcon_setup_lvds_phy(struct sun4i_tcon *tcon, + const struct drm_encoder *encoder) +{ + u8 val; + + regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, + SUN6I_TCON0_LVDS_ANA0_C(2) | + SUN6I_TCON0_LVDS_ANA0_V(3) | + SUN6I_TCON0_LVDS_ANA0_PD(2) | + SUN6I_TCON0_LVDS_ANA0_EN_LDO); + udelay(2); + + regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, + SUN6I_TCON0_LVDS_ANA0_EN_MB, + SUN6I_TCON0_LVDS_ANA0_EN_MB); + udelay(2); + + regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, + SUN6I_TCON0_LVDS_ANA0_EN_DRVC, + SUN6I_TCON0_LVDS_ANA0_EN_DRVC); + + if (sun4i_tcon_get_pixel_depth(encoder) == 18) + val = 7; + else + val = 0xf; + + regmap_write_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, + SUN6I_TCON0_LVDS_ANA0_EN_DRVD(0xf), + SUN6I_TCON0_LVDS_ANA0_EN_DRVD(val)); + +} + static void sun4i_tcon_lvds_set_status(struct sun4i_tcon *tcon, const struct drm_encoder *encoder, bool enabled) { if (enabled) { - u8 val; - regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, SUN4I_TCON0_LVDS_IF_EN, SUN4I_TCON0_LVDS_IF_EN); - - /* - * As their name suggest, these values only apply to the A31 - * and later SoCs. We'll have to rework this when merging - * support for the older SoCs. - */ - regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, - SUN6I_TCON0_LVDS_ANA0_C(2) | - SUN6I_TCON0_LVDS_ANA0_V(3) | - SUN6I_TCON0_LVDS_ANA0_PD(2) | - SUN6I_TCON0_LVDS_ANA0_EN_LDO); - udelay(2); - - regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, - SUN6I_TCON0_LVDS_ANA0_EN_MB, - SUN6I_TCON0_LVDS_ANA0_EN_MB); - udelay(2); - - regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, - SUN6I_TCON0_LVDS_ANA0_EN_DRVC, - SUN6I_TCON0_LVDS_ANA0_EN_DRVC); - - if (sun4i_tcon_get_pixel_depth(encoder) == 18) - val = 7; - else - val = 0xf; - - regmap_write_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, - SUN6I_TCON0_LVDS_ANA0_EN_DRVD(0xf), - SUN6I_TCON0_LVDS_ANA0_EN_DRVD(val)); + if (tcon->quirks->setup_lvds_phy) + tcon->quirks->setup_lvds_phy(tcon, encoder); } else { regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, SUN4I_TCON0_LVDS_IF_EN, 0); @@ -1465,12 +1467,14 @@ static const struct sun4i_tcon_quirks sun8i_a33_quirks = { .has_channel_0 = true, .has_lvds_alt = true, .dclk_min_div = 1, + .setup_lvds_phy = sun6i_tcon_setup_lvds_phy, }; static const struct sun4i_tcon_quirks sun8i_a83t_lcd_quirks = { .supports_lvds = true, .has_channel_0 = true, .dclk_min_div = 1, + .setup_lvds_phy = sun6i_tcon_setup_lvds_phy, }; static const struct sun4i_tcon_quirks sun8i_a83t_tv_quirks = { diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h index a62ec826ae71..2974e59ef9f2 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.h +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h @@ -228,6 +228,9 @@ struct sun4i_tcon_quirks { /* callback to handle tcon muxing options */ int (*set_mux)(struct sun4i_tcon *, const struct drm_encoder *); + /* handler for LVDS setup routine */ + void (*setup_lvds_phy)(struct sun4i_tcon *tcon, + const struct drm_encoder *encoder); }; struct sun4i_tcon { -- 2.20.1