From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: "Eric Auger" <eric.auger@redhat.com>,
"Aaron Lindsay" <aaron@os.amperecomputing.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Philippe Mathieu-Daudé" <philmd@redhat.com>
Subject: [PATCH v2 08/21] target/arm: Define an aa32_pmu_8_1 isar feature test function
Date: Fri, 14 Feb 2020 17:51:03 +0000 [thread overview]
Message-ID: <20200214175116.9164-9-peter.maydell@linaro.org> (raw)
In-Reply-To: <20200214175116.9164-1-peter.maydell@linaro.org>
Instead of open-coding a check on the ID_DFR0 PerfMon ID register
field, create a standardly-named isar_feature for "does AArch32 have
a v8.1 PMUv3" and use it.
This entails moving the id_dfr0 field into the ARMISARegisters struct.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 9 ++++++++-
hw/intc/armv7m_nvic.c | 2 +-
target/arm/cpu.c | 28 ++++++++++++++--------------
target/arm/cpu64.c | 6 +++---
target/arm/helper.c | 5 ++---
5 files changed, 28 insertions(+), 22 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 081955094dc..6c6088eb587 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -865,6 +865,7 @@ struct ARMCPU {
uint32_t mvfr0;
uint32_t mvfr1;
uint32_t mvfr2;
+ uint32_t id_dfr0;
uint64_t id_aa64isar0;
uint64_t id_aa64isar1;
uint64_t id_aa64pfr0;
@@ -880,7 +881,6 @@ struct ARMCPU {
uint32_t reset_sctlr;
uint32_t id_pfr0;
uint32_t id_pfr1;
- uint32_t id_dfr0;
uint64_t pmceid0;
uint64_t pmceid1;
uint32_t id_afr0;
@@ -3500,6 +3500,13 @@ static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id)
return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) >= 2;
}
+static inline bool isar_feature_aa32_pmu_8_1(const ARMISARegisters *id)
+{
+ /* 0xf means "non-standard IMPDEF PMU" */
+ return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 4 &&
+ FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
+}
+
/*
* 64-bit feature tests via id registers.
*/
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index f9e0eeaace6..5a403fc9704 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -1227,7 +1227,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
case 0xd44: /* PFR1. */
return cpu->id_pfr1;
case 0xd48: /* DFR0. */
- return cpu->id_dfr0;
+ return cpu->isar.id_dfr0;
case 0xd4c: /* AFR0. */
return cpu->id_afr0;
case 0xd50: /* MMFR0. */
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 1024f506c51..b85040d36bc 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1719,7 +1719,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
#endif
} else {
cpu->id_aa64dfr0 = FIELD_DP64(cpu->id_aa64dfr0, ID_AA64DFR0, PMUVER, 0);
- cpu->id_dfr0 = FIELD_DP32(cpu->id_dfr0, ID_DFR0, PERFMON, 0);
+ cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0);
cpu->pmceid0 = 0;
cpu->pmceid1 = 0;
}
@@ -1957,7 +1957,7 @@ static void arm1136_r2_initfn(Object *obj)
cpu->reset_sctlr = 0x00050078;
cpu->id_pfr0 = 0x111;
cpu->id_pfr1 = 0x1;
- cpu->id_dfr0 = 0x2;
+ cpu->isar.id_dfr0 = 0x2;
cpu->id_afr0 = 0x3;
cpu->id_mmfr0 = 0x01130003;
cpu->id_mmfr1 = 0x10030302;
@@ -1989,7 +1989,7 @@ static void arm1136_initfn(Object *obj)
cpu->reset_sctlr = 0x00050078;
cpu->id_pfr0 = 0x111;
cpu->id_pfr1 = 0x1;
- cpu->id_dfr0 = 0x2;
+ cpu->isar.id_dfr0 = 0x2;
cpu->id_afr0 = 0x3;
cpu->id_mmfr0 = 0x01130003;
cpu->id_mmfr1 = 0x10030302;
@@ -2022,7 +2022,7 @@ static void arm1176_initfn(Object *obj)
cpu->reset_sctlr = 0x00050078;
cpu->id_pfr0 = 0x111;
cpu->id_pfr1 = 0x11;
- cpu->id_dfr0 = 0x33;
+ cpu->isar.id_dfr0 = 0x33;
cpu->id_afr0 = 0;
cpu->id_mmfr0 = 0x01130003;
cpu->id_mmfr1 = 0x10030302;
@@ -2052,7 +2052,7 @@ static void arm11mpcore_initfn(Object *obj)
cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
cpu->id_pfr0 = 0x111;
cpu->id_pfr1 = 0x1;
- cpu->id_dfr0 = 0;
+ cpu->isar.id_dfr0 = 0;
cpu->id_afr0 = 0x2;
cpu->id_mmfr0 = 0x01100103;
cpu->id_mmfr1 = 0x10020302;
@@ -2084,7 +2084,7 @@ static void cortex_m3_initfn(Object *obj)
cpu->pmsav7_dregion = 8;
cpu->id_pfr0 = 0x00000030;
cpu->id_pfr1 = 0x00000200;
- cpu->id_dfr0 = 0x00100000;
+ cpu->isar.id_dfr0 = 0x00100000;
cpu->id_afr0 = 0x00000000;
cpu->id_mmfr0 = 0x00000030;
cpu->id_mmfr1 = 0x00000000;
@@ -2115,7 +2115,7 @@ static void cortex_m4_initfn(Object *obj)
cpu->isar.mvfr2 = 0x00000000;
cpu->id_pfr0 = 0x00000030;
cpu->id_pfr1 = 0x00000200;
- cpu->id_dfr0 = 0x00100000;
+ cpu->isar.id_dfr0 = 0x00100000;
cpu->id_afr0 = 0x00000000;
cpu->id_mmfr0 = 0x00000030;
cpu->id_mmfr1 = 0x00000000;
@@ -2146,7 +2146,7 @@ static void cortex_m7_initfn(Object *obj)
cpu->isar.mvfr2 = 0x00000040;
cpu->id_pfr0 = 0x00000030;
cpu->id_pfr1 = 0x00000200;
- cpu->id_dfr0 = 0x00100000;
+ cpu->isar.id_dfr0 = 0x00100000;
cpu->id_afr0 = 0x00000000;
cpu->id_mmfr0 = 0x00100030;
cpu->id_mmfr1 = 0x00000000;
@@ -2179,7 +2179,7 @@ static void cortex_m33_initfn(Object *obj)
cpu->isar.mvfr2 = 0x00000040;
cpu->id_pfr0 = 0x00000030;
cpu->id_pfr1 = 0x00000210;
- cpu->id_dfr0 = 0x00200000;
+ cpu->isar.id_dfr0 = 0x00200000;
cpu->id_afr0 = 0x00000000;
cpu->id_mmfr0 = 0x00101F40;
cpu->id_mmfr1 = 0x00000000;
@@ -2231,7 +2231,7 @@ static void cortex_r5_initfn(Object *obj)
cpu->midr = 0x411fc153; /* r1p3 */
cpu->id_pfr0 = 0x0131;
cpu->id_pfr1 = 0x001;
- cpu->id_dfr0 = 0x010400;
+ cpu->isar.id_dfr0 = 0x010400;
cpu->id_afr0 = 0x0;
cpu->id_mmfr0 = 0x0210030;
cpu->id_mmfr1 = 0x00000000;
@@ -2286,7 +2286,7 @@ static void cortex_a8_initfn(Object *obj)
cpu->reset_sctlr = 0x00c50078;
cpu->id_pfr0 = 0x1031;
cpu->id_pfr1 = 0x11;
- cpu->id_dfr0 = 0x400;
+ cpu->isar.id_dfr0 = 0x400;
cpu->id_afr0 = 0;
cpu->id_mmfr0 = 0x31100003;
cpu->id_mmfr1 = 0x20000000;
@@ -2359,7 +2359,7 @@ static void cortex_a9_initfn(Object *obj)
cpu->reset_sctlr = 0x00c50078;
cpu->id_pfr0 = 0x1031;
cpu->id_pfr1 = 0x11;
- cpu->id_dfr0 = 0x000;
+ cpu->isar.id_dfr0 = 0x000;
cpu->id_afr0 = 0;
cpu->id_mmfr0 = 0x00100103;
cpu->id_mmfr1 = 0x20000000;
@@ -2424,7 +2424,7 @@ static void cortex_a7_initfn(Object *obj)
cpu->reset_sctlr = 0x00c50078;
cpu->id_pfr0 = 0x00001131;
cpu->id_pfr1 = 0x00011011;
- cpu->id_dfr0 = 0x02010555;
+ cpu->isar.id_dfr0 = 0x02010555;
cpu->id_afr0 = 0x00000000;
cpu->id_mmfr0 = 0x10101105;
cpu->id_mmfr1 = 0x40000000;
@@ -2470,7 +2470,7 @@ static void cortex_a15_initfn(Object *obj)
cpu->reset_sctlr = 0x00c50078;
cpu->id_pfr0 = 0x00001131;
cpu->id_pfr1 = 0x00011011;
- cpu->id_dfr0 = 0x02010555;
+ cpu->isar.id_dfr0 = 0x02010555;
cpu->id_afr0 = 0x00000000;
cpu->id_mmfr0 = 0x10201105;
cpu->id_mmfr1 = 0x20000000;
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index f0d98bc79d1..9e4387158f9 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -121,7 +121,7 @@ static void aarch64_a57_initfn(Object *obj)
cpu->reset_sctlr = 0x00c50838;
cpu->id_pfr0 = 0x00000131;
cpu->id_pfr1 = 0x00011011;
- cpu->id_dfr0 = 0x03010066;
+ cpu->isar.id_dfr0 = 0x03010066;
cpu->id_afr0 = 0x00000000;
cpu->id_mmfr0 = 0x10101105;
cpu->id_mmfr1 = 0x40000000;
@@ -175,7 +175,7 @@ static void aarch64_a53_initfn(Object *obj)
cpu->reset_sctlr = 0x00c50838;
cpu->id_pfr0 = 0x00000131;
cpu->id_pfr1 = 0x00011011;
- cpu->id_dfr0 = 0x03010066;
+ cpu->isar.id_dfr0 = 0x03010066;
cpu->id_afr0 = 0x00000000;
cpu->id_mmfr0 = 0x10101105;
cpu->id_mmfr1 = 0x40000000;
@@ -228,7 +228,7 @@ static void aarch64_a72_initfn(Object *obj)
cpu->reset_sctlr = 0x00c50838;
cpu->id_pfr0 = 0x00000131;
cpu->id_pfr1 = 0x00011011;
- cpu->id_dfr0 = 0x03010066;
+ cpu->isar.id_dfr0 = 0x03010066;
cpu->id_afr0 = 0x00000000;
cpu->id_mmfr0 = 0x10201105;
cpu->id_mmfr1 = 0x40000000;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 376c6412f91..048e541eda4 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6381,8 +6381,7 @@ static void define_pmu_regs(ARMCPU *cpu)
g_free(pmevtyper_name);
g_free(pmevtyper_el0_name);
}
- if (FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) >= 4 &&
- FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) != 0xf) {
+ if (cpu_isar_feature(aa32_pmu_8_1, cpu)) {
ARMCPRegInfo v81_pmu_regs[] = {
{ .name = "PMCEID2", .state = ARM_CP_STATE_AA32,
.cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 4,
@@ -6856,7 +6855,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa32_tid3,
- .resetvalue = cpu->id_dfr0 },
+ .resetvalue = cpu->isar.id_dfr0 },
{ .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
.access = PL1_R, .type = ARM_CP_CONST,
--
2.20.1
next prev parent reply other threads:[~2020-02-14 17:52 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-14 17:50 [PATCH v2 00/21] arm: ARMv8.1- and v8.4-PMU, ID reg cleanup, [H]ACTLR2 Peter Maydell
2020-02-14 17:50 ` [PATCH v2 01/21] target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registers Peter Maydell
2020-02-14 17:50 ` [PATCH v2 02/21] target/arm: Check aa32_pan in take_aarch32_exception(), not aa64_pan Peter Maydell
2020-02-14 20:10 ` Richard Henderson
2020-02-14 17:50 ` [PATCH v2 03/21] target/arm: Add isar_feature_any_fp16 and document naming/usage conventions Peter Maydell
2020-02-14 17:50 ` [PATCH v2 04/21] target/arm: Define and use any_predinv isar_feature test Peter Maydell
2020-02-14 17:51 ` [PATCH v2 05/21] target/arm: Factor out PMU register definitions Peter Maydell
2020-02-14 17:51 ` [PATCH v2 06/21] target/arm: Add and use FIELD definitions for ID_AA64DFR0_EL1 Peter Maydell
2020-02-14 17:51 ` [PATCH v2 07/21] target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON field Peter Maydell
2020-02-14 17:51 ` Peter Maydell [this message]
2020-02-14 17:51 ` [PATCH v2 09/21] target/arm: Add _aa64_ and _any_ versions of pmu_8_1 isar checks Peter Maydell
2020-02-14 17:51 ` [PATCH v2 10/21] target/arm: Stop assuming DBGDIDR always exists Peter Maydell
2020-02-14 20:15 ` Richard Henderson
2020-02-14 17:51 ` [PATCH v2 11/21] target/arm: Move DBGDIDR into ARMISARegisters Peter Maydell
2020-02-14 20:16 ` Richard Henderson
2020-02-14 17:51 ` [PATCH v2 12/21] target/arm: Read debug-related ID registers from KVM Peter Maydell
2020-02-14 20:27 ` Richard Henderson
2020-02-14 17:51 ` [PATCH v2 13/21] target/arm: Implement ARMv8.1-PMU extension Peter Maydell
2020-02-14 17:51 ` [PATCH v2 14/21] target/arm: Implement ARMv8.4-PMU extension Peter Maydell
2020-02-14 17:51 ` [PATCH v2 15/21] target/arm: Provide ARMv8.4-PMU in '-cpu max' Peter Maydell
2020-02-14 17:51 ` [PATCH v2 16/21] target/arm: Correct definition of PMCRDP Peter Maydell
2020-02-14 17:51 ` [PATCH v2 17/21] target/arm: Correct handling of PMCR_EL0.LC bit Peter Maydell
2020-02-14 17:51 ` [PATCH v2 18/21] target/arm: Test correct register in aa32_pan and aa32_ats1e1 checks Peter Maydell
2020-02-14 20:30 ` Richard Henderson
2020-02-14 17:51 ` [PATCH v2 19/21] target/arm: Use isar_feature function for testing AA32HPD feature Peter Maydell
2020-02-14 20:32 ` Richard Henderson
2020-02-14 17:51 ` [PATCH v2 20/21] target/arm: Use FIELD_EX32 for testing 32-bit fields Peter Maydell
2020-02-14 20:32 ` Richard Henderson
2020-02-14 17:51 ` [PATCH v2 21/21] target/arm: Correctly implement ACTLR2, HACTLR2 Peter Maydell
2020-02-14 20:42 ` Richard Henderson
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