From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linutronix.de (193.142.43.55:993) by crypto-ml.lab.linutronix.de with IMAP4-SSL for ; 20 Feb 2020 10:08:02 -0000 Received: from mx2.suse.de ([195.135.220.15]) by Galois.linutronix.de with esmtps (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1j4ikT-0005Ps-FY for speck@linutronix.de; Thu, 20 Feb 2020 11:08:01 +0100 Received: from relay2.suse.de (unknown [195.135.220.254]) by mx2.suse.de (Postfix) with ESMTP id D74A6B1B8 for ; Thu, 20 Feb 2020 10:07:54 +0000 (UTC) Date: Thu, 20 Feb 2020 11:07:45 +0100 From: Borislav Petkov Subject: [MODERATED] Re: [PATCH 1/2] more sampling fun 1 Message-ID: <20200220100745.GA30404@zn.tnic> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable To: speck@linutronix.de List-ID: On Thu, Feb 06, 2020 at 02:11:02PM -0800, speck for mark gross wrote: > From: mark gross > Subject: [PATCH 1/2] Add capability to specify a range of steppings in the >=20 > Intel has produced processors with the same CPUID family+model. Code > may need to check the stepping when programming model specific behavior. >=20 > Add an API to allow easy specification of stepping or range of steppings > with a 16 bit bitmask. >=20 > Update cpu_vuln_whitelist using this new API. >=20 > I implemented this in the way I did to avoid modifying x86_cpu_id as > that structure is an exported ABI and any change would impact user mode > code using the structure. >=20 > Signed-off-by: mark gross > Reviewed-by: tony luck > --- > arch/x86/include/asm/cpu_device_id.h | 12 ++++++++++++ > arch/x86/kernel/cpu/common.c | 28 ++++++++++++++-------------- > arch/x86/kernel/cpu/match.c | 26 ++++++++++++++++++++++++++ > 3 files changed, 52 insertions(+), 14 deletions(-) Why isn't this sent to lkml like a normal patch? --=20 Regards/Gruss, Boris. SUSE Software Solutions Germany GmbH, GF: Felix Imend=C3=B6rffer, HRB 36809, = AG N=C3=BCrnberg --=20