From: "Michael S. Tsirkin" <mst@redhat.com>
To: Yubo Miao <miaoyubo@huawei.com>
Cc: peter.maydell@linaro.org, imammedo@redhat.com,
qemu-devel@nongnu.org, xiexiangyou@huawei.com,
shannon.zhaosl@gmail.com
Subject: Re: [RFC v3 2/3] acpi:pci-expender-bus: Add pxb support for arm
Date: Fri, 21 Feb 2020 06:17:48 -0500 [thread overview]
Message-ID: <20200221061402-mutt-send-email-mst@kernel.org> (raw)
In-Reply-To: <20200221063512.1104-3-miaoyubo@huawei.com>
On Fri, Feb 21, 2020 at 02:35:11PM +0800, Yubo Miao wrote:
> From: miaoyubo <miaoyubo@huawei.com>
>
> Currently virt machine is not supported by pxb-pcie,
> and only one main host bridge described in ACPI tables.
> In this patch,PXB-PCIE is supproted by arm and certain
> resource is allocated for each pxb-pcie in acpi table.
> The resource for the main host bridge is also reallocated.
>
> Signed-off-by: miaoyubo <miaoyubo@huawei.com>
> ---
> hw/arm/virt-acpi-build.c | 125 +++++++++++++++++++++++++++++++++++----
> hw/pci-host/gpex.c | 4 ++
> include/hw/arm/virt.h | 7 +++
> 3 files changed, 125 insertions(+), 11 deletions(-)
>
> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> index 0540234b8a..2c1e0d2aaa 100644
> --- a/hw/arm/virt-acpi-build.c
> +++ b/hw/arm/virt-acpi-build.c
> @@ -49,6 +49,8 @@
> #include "kvm_arm.h"
> #include "migration/vmstate.h"
>
> +#include "hw/arm/virt.h"
> +#include "hw/pci/pci_bus.h"
> #define ARM_SPI_BASE 32
>
> static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus)
> @@ -271,19 +273,117 @@ static void acpi_dsdt_add_pci_osc(Aml *dev, Aml *scope)
> }
>
> static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
> - uint32_t irq, bool use_highmem, bool highmem_ecam)
> + uint32_t irq, bool use_highmem, bool highmem_ecam,
> + VirtMachineState *vms)
> {
> int ecam_id = VIRT_ECAM_ID(highmem_ecam);
> - Aml *method, *crs;
> + Aml *method, *dev, *crs;
> + int count = 0;
> hwaddr base_mmio = memmap[VIRT_PCIE_MMIO].base;
> hwaddr size_mmio = memmap[VIRT_PCIE_MMIO].size;
> hwaddr base_pio = memmap[VIRT_PCIE_PIO].base;
> hwaddr size_pio = memmap[VIRT_PCIE_PIO].size;
> hwaddr base_ecam = memmap[ecam_id].base;
> hwaddr size_ecam = memmap[ecam_id].size;
> + /*
> + * 0x600000 would be enough for pxb device
> + * if it is too small, there is no enough space
> + * for a pcie device plugged in a pcie-root port
> + */
> + hwaddr size_addr = 0x600000;
> + hwaddr size_io = 0x4000;
> int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
> + int root_bus_limit = 0xFF;
what's this?
> + PCIBus *bus = NULL;
> + bus = VIRT_MACHINE(vms)->bus;
So just move assignment as part of declaration.
> +
> + if (bus) {
> + QLIST_FOREACH(bus, &bus->child, sibling) {
> + uint8_t bus_num = pci_bus_num(bus);
> + uint8_t numa_node = pci_bus_numa_node(bus);
> +
> + if (!pci_bus_is_root(bus)) {
> + continue;
> + }
> + if (bus_num < root_bus_limit) {
> + root_bus_limit = bus_num - 1;
what is this doing? manually coded up MIN?
> + }
> + count++;
> + dev = aml_device("PC%.02X", bus_num);
> + aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
> + aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
> + aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
> + aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
> + aml_append(dev, aml_name_decl("_SEG", aml_int(0)));
> + aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
> + aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
> + aml_append(dev, aml_name_decl("_STR", aml_unicode("pxb Device")));
> + if (numa_node != NUMA_NODE_UNASSIGNED) {
> + method = aml_method("_PXM", 0, AML_NOTSERIALIZED);
> + aml_append(method, aml_return(aml_int(numa_node)));
> + aml_append(dev, method);
> + }
> +
> + acpi_dsdt_add_pci_route_table(dev, scope, nr_pcie_buses, irq);
> +
> + method = aml_method("_CBA", 0, AML_NOTSERIALIZED);
> + aml_append(method, aml_return(aml_int(base_ecam)));
> + aml_append(dev, method);
> +
> + method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
> + Aml *rbuf = aml_resource_template();
> + aml_append(rbuf,
> + aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED,
> + AML_POS_DECODE, 0x0000,
> + bus_num, bus_num + 1, 0x0000,
> + 2));
> + aml_append(rbuf,
> + aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
> + AML_MAX_FIXED, AML_NON_CACHEABLE,
> + AML_READ_WRITE, 0x0000,
> + base_mmio + size_mmio -
> + size_addr * count,
> + base_mmio + size_mmio - 1 -
> + size_addr * (count - 1),
> + 0x0000, size_addr));
> + aml_append(rbuf,
> + aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED,
> + AML_POS_DECODE, AML_ENTIRE_RANGE,
> + 0x0000, size_pio - size_io * count,
> + size_pio - 1 - size_io * (count - 1),
> + base_pio, size_io));
> +
> + if (use_highmem) {
> + hwaddr base_mmio_high = memmap[VIRT_HIGH_PCIE_MMIO].base;
> + hwaddr size_mmio_high = memmap[VIRT_HIGH_PCIE_MMIO].size;
> +
> + aml_append(rbuf,
> + aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
> + AML_MAX_FIXED, AML_NON_CACHEABLE,
> + AML_READ_WRITE, 0x0000,
> + base_mmio_high + size_mmio_high -
> + size_addr * count,
> + base_mmio_high + size_mmio_high -
> + 1 - size_addr * (count - 1),
> + 0x0000, size_addr));
> + }
> +
> + aml_append(method, aml_name_decl("RBUF", rbuf));
> + aml_append(method, aml_return(rbuf));
> + aml_append(dev, method);
> +
> + acpi_dsdt_add_pci_osc(dev, scope);
> +
> + Aml *dev_rp0 = aml_device("%s", "RP0");
> + aml_append(dev_rp0, aml_name_decl("_ADR", aml_int(0)));
> + aml_append(dev, dev_rp0);
> +
> + aml_append(scope, dev);
> +
> + }
> + }
>
> - Aml *dev = aml_device("%s", "PCI0");
> + dev = aml_device("%s", "PCI0");
> aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
> aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
> aml_append(dev, aml_name_decl("_SEG", aml_int(0)));
> @@ -303,16 +403,18 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
> Aml *rbuf = aml_resource_template();
> aml_append(rbuf,
> aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
> - 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000,
> - nr_pcie_buses));
> + 0x0000, 0x0000, root_bus_limit, 0x0000,
> + root_bus_limit + 1));
> aml_append(rbuf,
> aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
> AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_mmio,
> - base_mmio + size_mmio - 1, 0x0000, size_mmio));
> + base_mmio + size_mmio - 1 - size_addr * count,
> + 0x0000, size_mmio - size_addr * count));
> aml_append(rbuf,
> aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
> - AML_ENTIRE_RANGE, 0x0000, 0x0000, size_pio - 1, base_pio,
> - size_pio));
> + AML_ENTIRE_RANGE, 0x0000, 0x0000,
> + size_pio - 1 - size_io * count, base_pio,
> + size_pio - size_io * count));
>
> if (use_highmem) {
> hwaddr base_mmio_high = memmap[VIRT_HIGH_PCIE_MMIO].base;
> @@ -322,8 +424,9 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
> aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
> AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
> base_mmio_high,
> - base_mmio_high + size_mmio_high - 1, 0x0000,
> - size_mmio_high));
> + base_mmio_high + size_mmio_high - 1 -
> + size_addr * count,
> + 0x0000, size_mmio_high - size_addr * count));
> }
>
> aml_append(method, aml_name_decl("RBUF", rbuf));
> @@ -759,7 +862,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
> acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO],
> (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS);
> acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE),
> - vms->highmem, vms->highmem_ecam);
> + vms->highmem, vms->highmem_ecam, vms);
> if (vms->acpi_dev) {
> build_ged_aml(scope, "\\_SB."GED_DEVICE,
> HOTPLUG_HANDLER(vms->acpi_dev),
> diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c
> index 0ca604dc62..2c18cdfec4 100644
> --- a/hw/pci-host/gpex.c
> +++ b/hw/pci-host/gpex.c
> @@ -36,6 +36,7 @@
> #include "hw/qdev-properties.h"
> #include "migration/vmstate.h"
> #include "qemu/module.h"
> +#include "hw/arm/virt.h"
>
> /****************************************************************************
> * GPEX host
> @@ -98,6 +99,9 @@ static void gpex_host_realize(DeviceState *dev, Error **errp)
> pci_swizzle_map_irq_fn, s, &s->io_mmio,
> &s->io_ioport, 0, 4, TYPE_PCIE_BUS);
>
> +#ifdef __aarch64__
> + VIRT_MACHINE(qdev_get_machine())->bus = pci->bus;
> +#endif
I'm repeating myself but - what does this have to do with
building on __aarch64__?
> qdev_set_parent_bus(DEVICE(&s->gpex_root), BUS(pci->bus));
> pci_bus_set_route_irq_fn(pci->bus, gpex_route_intx_pin_to_irq);
> qdev_init_nofail(DEVICE(&s->gpex_root));
> diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
> index 71508bf40c..9accaf2b1b 100644
> --- a/include/hw/arm/virt.h
> +++ b/include/hw/arm/virt.h
> @@ -140,6 +140,13 @@ typedef struct {
> DeviceState *gic;
> DeviceState *acpi_dev;
> Notifier powerdown_notifier;
> + /*
> + * pointer to devices and objects
> + * Via going through the bus, all
> + * pci devices and related objectes
> + * could be gained.
> + * */
> + PCIBus *bus;
That comment doesn't really tell me what this is.
Is this the root bus?
With an extender, don't we have lots of roots?
> } VirtMachineState;
>
> #define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM)
> --
> 2.19.1
>
next prev parent reply other threads:[~2020-02-21 11:18 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-21 6:35 [RFC v3 0/3] pci_expander_brdige:acpi:Support pxb-pcie for ARM Yubo Miao
2020-02-21 6:35 ` [RFC v3 1/3] acpi:Extract two APIs from acpi_dsdt_add_pci Yubo Miao
2020-02-21 6:35 ` [RFC v3 2/3] acpi:pci-expender-bus: Add pxb support for arm Yubo Miao
2020-02-21 11:17 ` Michael S. Tsirkin [this message]
2020-02-22 9:37 ` miaoyubo
2020-02-21 6:35 ` [RFC v3 3/3] ACPI/unit-test: Add a new test for pxb-pcie " Yubo Miao
2020-02-21 11:19 ` Michael S. Tsirkin
2020-02-22 9:40 ` miaoyubo
2020-02-23 21:25 ` Michael S. Tsirkin
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