Re: Emulating Solaris 10 on SPARC64 sun4u

["Dr. David Alan Gilbert" <dgilbert@redhat.com>]

* BALATON Zoltan (balaton@eik.bme.hu) wrote:
> On Wed, 19 Feb 2020, BALATON Zoltan wrote:
> > faster or doing something differently? Does someone know what interrupts
> > are generated on real hardware in DMA mode so we can compare that to
> > what we see with QEMU?
> 
> The document Programming Interface for Bus Master IDE Controller, Revision
> 1.0 (5/16/94) has some info on this. AFAIU it says that after DMA operation
> is completed an IRQ should be raised. On page 5, section 3.1. Data
> Synchronization it says:
> 
> "Another way to view this requirement is that the first read to the
> controller Status register in response to the IDE device interrupt must
> return with the Interrupt bit set and with the guarantee that all buffered
> data has been written to memory."
> 
> Not sure if this is relevant but how is it handled in QEMU? Is the right
> interrupt bit set after DMA transfer is done? If so is it the one that's
> checked by the OS driver?

One thing to be a little careful of is I remember the 646 was always
known for having a few quirks (I've not got a SPARC64 ith one, but I
think my Alpha has it).  So whether you're chasing a generic IDE BM
problem or a 646 special is fun.

Dave

> Regards,
> BALATON Zoltan
> 
--
Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK