diff for duplicates of <20200225201415.431668-1-msbarth@linux.ibm.com> diff --git a/a/1.txt b/N1/1.txt index 7305e3e..db16b06 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -24,82 +24,82 @@ index c63cefce636d..d9fa9fd48058 100644 model = "Rainier"; @@ -351,66 +352,82 @@ - gpio at 0 { + gpio@0 { reg = <0>; + type = <PCA955X_TYPE_GPIO>; }; - gpio at 1 { + gpio@1 { reg = <1>; + type = <PCA955X_TYPE_GPIO>; }; - gpio at 2 { + gpio@2 { reg = <2>; + type = <PCA955X_TYPE_GPIO>; }; - gpio at 3 { + gpio@3 { reg = <3>; + type = <PCA955X_TYPE_GPIO>; }; - gpio at 4 { + gpio@4 { reg = <4>; + type = <PCA955X_TYPE_GPIO>; }; - gpio at 5 { + gpio@5 { reg = <5>; + type = <PCA955X_TYPE_GPIO>; }; - gpio at 6 { + gpio@6 { reg = <6>; + type = <PCA955X_TYPE_GPIO>; }; - gpio at 7 { + gpio@7 { reg = <7>; + type = <PCA955X_TYPE_GPIO>; }; - gpio at 8 { + gpio@8 { reg = <8>; + type = <PCA955X_TYPE_GPIO>; }; - gpio at 9 { + gpio@9 { reg = <9>; + type = <PCA955X_TYPE_GPIO>; }; - gpio at 10 { + gpio@10 { reg = <10>; + type = <PCA955X_TYPE_GPIO>; }; - gpio at 11 { + gpio@11 { reg = <11>; + type = <PCA955X_TYPE_GPIO>; }; - gpio at 12 { + gpio@12 { reg = <12>; + type = <PCA955X_TYPE_GPIO>; }; - gpio at 13 { + gpio@13 { reg = <13>; + type = <PCA955X_TYPE_GPIO>; }; - gpio at 14 { + gpio@14 { reg = <14>; + type = <PCA955X_TYPE_GPIO>; }; - gpio at 15 { + gpio@15 { reg = <15>; + type = <PCA955X_TYPE_GPIO>; }; diff --git a/a/content_digest b/N1/content_digest index 72708ae..bb788b6 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,7 +1,15 @@ "From\0Matthew Barth <msbarth@linux.ibm.com>\0" "Subject\0[PATCH v2] ARM: dts: rainier: Set PCA9552 pin types\0" "Date\0Tue, 25 Feb 2020 14:14:15 -0600\0" - "To\0linux-aspeed@lists.ozlabs.org\0" + "To\0Joel Stanley <joel@jms.id.au>" + Andrew Jeffery <andrew@aj.id.au> + openbmc@lists.ozlabs.org + devicetree@vger.kernel.org + linux-arm-kernel@lists.infradead.org + linux-aspeed@lists.ozlabs.org + linux-kernel@vger.kernel.org + Brandon Wyman <bjwyman@gmail.com> + " Eddie James <eajames@linux.ibm.com>\0" "\00:1\0" "b\0" "All 16 pins of the PCA9552 at 7-bit address 0x61 should be set as type\n" @@ -30,82 +38,82 @@ " \tmodel = \"Rainier\";\n" "@@ -351,66 +352,82 @@\n" " \n" - " \t\tgpio at 0 {\n" + " \t\tgpio@0 {\n" " \t\t\treg = <0>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" " \t\t};\n" " \n" - " \t\tgpio at 1 {\n" + " \t\tgpio@1 {\n" " \t\t\treg = <1>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" " \t\t};\n" " \n" - " \t\tgpio at 2 {\n" + " \t\tgpio@2 {\n" " \t\t\treg = <2>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" " \t\t};\n" " \n" - " \t\tgpio at 3 {\n" + " \t\tgpio@3 {\n" " \t\t\treg = <3>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" " \t\t};\n" " \n" - " \t\tgpio at 4 {\n" + " \t\tgpio@4 {\n" " \t\t\treg = <4>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" " \t\t};\n" " \n" - " \t\tgpio at 5 {\n" + " \t\tgpio@5 {\n" " \t\t\treg = <5>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" " \t\t};\n" " \n" - " \t\tgpio at 6 {\n" + " \t\tgpio@6 {\n" " \t\t\treg = <6>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" " \t\t};\n" " \n" - " \t\tgpio at 7 {\n" + " \t\tgpio@7 {\n" " \t\t\treg = <7>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" " \t\t};\n" " \n" - " \t\tgpio at 8 {\n" + " \t\tgpio@8 {\n" " \t\t\treg = <8>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" " \t\t};\n" " \n" - " \t\tgpio at 9 {\n" + " \t\tgpio@9 {\n" " \t\t\treg = <9>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" " \t\t};\n" " \n" - " \t\tgpio at 10 {\n" + " \t\tgpio@10 {\n" " \t\t\treg = <10>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" " \t\t};\n" " \n" - " \t\tgpio at 11 {\n" + " \t\tgpio@11 {\n" " \t\t\treg = <11>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" " \t\t};\n" " \n" - " \t\tgpio at 12 {\n" + " \t\tgpio@12 {\n" " \t\t\treg = <12>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" " \t\t};\n" " \n" - " \t\tgpio at 13 {\n" + " \t\tgpio@13 {\n" " \t\t\treg = <13>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" " \t\t};\n" " \n" - " \t\tgpio at 14 {\n" + " \t\tgpio@14 {\n" " \t\t\treg = <14>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" " \t\t};\n" " \n" - " \t\tgpio at 15 {\n" + " \t\tgpio@15 {\n" " \t\t\treg = <15>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" " \t\t};\n" @@ -114,4 +122,4 @@ "-- \n" 2.24.1 -ddddbd78d76a9f90ce646d1c64cb606ab1c175a2e00c9a45b3f4e3311de8af36 +e55fb6d37c33e9417dc91a20483fb23a62640b5df0e88809070561c9476df813
diff --git a/a/1.txt b/N2/1.txt index 7305e3e..babb460 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -24,82 +24,82 @@ index c63cefce636d..d9fa9fd48058 100644 model = "Rainier"; @@ -351,66 +352,82 @@ - gpio at 0 { + gpio@0 { reg = <0>; + type = <PCA955X_TYPE_GPIO>; }; - gpio at 1 { + gpio@1 { reg = <1>; + type = <PCA955X_TYPE_GPIO>; }; - gpio at 2 { + gpio@2 { reg = <2>; + type = <PCA955X_TYPE_GPIO>; }; - gpio at 3 { + gpio@3 { reg = <3>; + type = <PCA955X_TYPE_GPIO>; }; - gpio at 4 { + gpio@4 { reg = <4>; + type = <PCA955X_TYPE_GPIO>; }; - gpio at 5 { + gpio@5 { reg = <5>; + type = <PCA955X_TYPE_GPIO>; }; - gpio at 6 { + gpio@6 { reg = <6>; + type = <PCA955X_TYPE_GPIO>; }; - gpio at 7 { + gpio@7 { reg = <7>; + type = <PCA955X_TYPE_GPIO>; }; - gpio at 8 { + gpio@8 { reg = <8>; + type = <PCA955X_TYPE_GPIO>; }; - gpio at 9 { + gpio@9 { reg = <9>; + type = <PCA955X_TYPE_GPIO>; }; - gpio at 10 { + gpio@10 { reg = <10>; + type = <PCA955X_TYPE_GPIO>; }; - gpio at 11 { + gpio@11 { reg = <11>; + type = <PCA955X_TYPE_GPIO>; }; - gpio at 12 { + gpio@12 { reg = <12>; + type = <PCA955X_TYPE_GPIO>; }; - gpio at 13 { + gpio@13 { reg = <13>; + type = <PCA955X_TYPE_GPIO>; }; - gpio at 14 { + gpio@14 { reg = <14>; + type = <PCA955X_TYPE_GPIO>; }; - gpio at 15 { + gpio@15 { reg = <15>; + type = <PCA955X_TYPE_GPIO>; }; @@ -107,3 +107,9 @@ index c63cefce636d..d9fa9fd48058 100644 -- 2.24.1 + + +_______________________________________________ +linux-arm-kernel mailing list +linux-arm-kernel@lists.infradead.org +http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/a/content_digest b/N2/content_digest index 72708ae..65e84a9 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,7 +1,16 @@ "From\0Matthew Barth <msbarth@linux.ibm.com>\0" "Subject\0[PATCH v2] ARM: dts: rainier: Set PCA9552 pin types\0" "Date\0Tue, 25 Feb 2020 14:14:15 -0600\0" - "To\0linux-aspeed@lists.ozlabs.org\0" + "To\0Joel Stanley <joel@jms.id.au>" + Andrew Jeffery <andrew@aj.id.au> + openbmc@lists.ozlabs.org + devicetree@vger.kernel.org + linux-arm-kernel@lists.infradead.org + linux-aspeed@lists.ozlabs.org + linux-kernel@vger.kernel.org + Brandon Wyman <bjwyman@gmail.com> + " Eddie James <eajames@linux.ibm.com>\0" + "Cc\0Matthew Barth <msbarth@linux.ibm.com>\0" "\00:1\0" "b\0" "All 16 pins of the PCA9552 at 7-bit address 0x61 should be set as type\n" @@ -30,88 +39,94 @@ " \tmodel = \"Rainier\";\n" "@@ -351,66 +352,82 @@\n" " \n" - " \t\tgpio at 0 {\n" + " \t\tgpio@0 {\n" " \t\t\treg = <0>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" " \t\t};\n" " \n" - " \t\tgpio at 1 {\n" + " \t\tgpio@1 {\n" " \t\t\treg = <1>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" " \t\t};\n" " \n" - " \t\tgpio at 2 {\n" + " \t\tgpio@2 {\n" " \t\t\treg = <2>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" " \t\t};\n" " \n" - " \t\tgpio at 3 {\n" + " \t\tgpio@3 {\n" " \t\t\treg = <3>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" " \t\t};\n" " \n" - " \t\tgpio at 4 {\n" + " \t\tgpio@4 {\n" " \t\t\treg = <4>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" " \t\t};\n" " \n" - " \t\tgpio at 5 {\n" + " \t\tgpio@5 {\n" " \t\t\treg = <5>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" " \t\t};\n" " \n" - " \t\tgpio at 6 {\n" + " \t\tgpio@6 {\n" " \t\t\treg = <6>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" " \t\t};\n" " \n" - " \t\tgpio at 7 {\n" + " \t\tgpio@7 {\n" " \t\t\treg = <7>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" " \t\t};\n" " \n" - " \t\tgpio at 8 {\n" + " \t\tgpio@8 {\n" " \t\t\treg = <8>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" " \t\t};\n" " \n" - " \t\tgpio at 9 {\n" + " \t\tgpio@9 {\n" " \t\t\treg = <9>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" " \t\t};\n" " \n" - " \t\tgpio at 10 {\n" + " \t\tgpio@10 {\n" " \t\t\treg = <10>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" " \t\t};\n" " \n" - " \t\tgpio at 11 {\n" + " \t\tgpio@11 {\n" " \t\t\treg = <11>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" " \t\t};\n" " \n" - " \t\tgpio at 12 {\n" + " \t\tgpio@12 {\n" " \t\t\treg = <12>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" " \t\t};\n" " \n" - " \t\tgpio at 13 {\n" + " \t\tgpio@13 {\n" " \t\t\treg = <13>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" " \t\t};\n" " \n" - " \t\tgpio at 14 {\n" + " \t\tgpio@14 {\n" " \t\t\treg = <14>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" " \t\t};\n" " \n" - " \t\tgpio at 15 {\n" + " \t\tgpio@15 {\n" " \t\t\treg = <15>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" " \t\t};\n" " \t};\n" " \n" "-- \n" - 2.24.1 + "2.24.1\n" + "\n" + "\n" + "_______________________________________________\n" + "linux-arm-kernel mailing list\n" + "linux-arm-kernel@lists.infradead.org\n" + http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -ddddbd78d76a9f90ce646d1c64cb606ab1c175a2e00c9a45b3f4e3311de8af36 +90454af588ee58ec0c37d2f4b307770f824084d2ae5edc030abe36f71abf9d55
diff --git a/a/1.txt b/N3/1.txt index 7305e3e..db16b06 100644 --- a/a/1.txt +++ b/N3/1.txt @@ -24,82 +24,82 @@ index c63cefce636d..d9fa9fd48058 100644 model = "Rainier"; @@ -351,66 +352,82 @@ - gpio at 0 { + gpio@0 { reg = <0>; + type = <PCA955X_TYPE_GPIO>; }; - gpio at 1 { + gpio@1 { reg = <1>; + type = <PCA955X_TYPE_GPIO>; }; - gpio at 2 { + gpio@2 { reg = <2>; + type = <PCA955X_TYPE_GPIO>; }; - gpio at 3 { + gpio@3 { reg = <3>; + type = <PCA955X_TYPE_GPIO>; }; - gpio at 4 { + gpio@4 { reg = <4>; + type = <PCA955X_TYPE_GPIO>; }; - gpio at 5 { + gpio@5 { reg = <5>; + type = <PCA955X_TYPE_GPIO>; }; - gpio at 6 { + gpio@6 { reg = <6>; + type = <PCA955X_TYPE_GPIO>; }; - gpio at 7 { + gpio@7 { reg = <7>; + type = <PCA955X_TYPE_GPIO>; }; - gpio at 8 { + gpio@8 { reg = <8>; + type = <PCA955X_TYPE_GPIO>; }; - gpio at 9 { + gpio@9 { reg = <9>; + type = <PCA955X_TYPE_GPIO>; }; - gpio at 10 { + gpio@10 { reg = <10>; + type = <PCA955X_TYPE_GPIO>; }; - gpio at 11 { + gpio@11 { reg = <11>; + type = <PCA955X_TYPE_GPIO>; }; - gpio at 12 { + gpio@12 { reg = <12>; + type = <PCA955X_TYPE_GPIO>; }; - gpio at 13 { + gpio@13 { reg = <13>; + type = <PCA955X_TYPE_GPIO>; }; - gpio at 14 { + gpio@14 { reg = <14>; + type = <PCA955X_TYPE_GPIO>; }; - gpio at 15 { + gpio@15 { reg = <15>; + type = <PCA955X_TYPE_GPIO>; }; diff --git a/a/content_digest b/N3/content_digest index 72708ae..b81049f 100644 --- a/a/content_digest +++ b/N3/content_digest @@ -1,7 +1,16 @@ "From\0Matthew Barth <msbarth@linux.ibm.com>\0" "Subject\0[PATCH v2] ARM: dts: rainier: Set PCA9552 pin types\0" "Date\0Tue, 25 Feb 2020 14:14:15 -0600\0" - "To\0linux-aspeed@lists.ozlabs.org\0" + "To\0Joel Stanley <joel@jms.id.au>" + Andrew Jeffery <andrew@aj.id.au> + openbmc@lists.ozlabs.org + devicetree@vger.kernel.org + linux-arm-kernel@lists.infradead.org + linux-aspeed@lists.ozlabs.org + linux-kernel@vger.kernel.org + Brandon Wyman <bjwyman@gmail.com> + " Eddie James <eajames@linux.ibm.com>\0" + "Cc\0Matthew Barth <msbarth@linux.ibm.com>\0" "\00:1\0" "b\0" "All 16 pins of the PCA9552 at 7-bit address 0x61 should be set as type\n" @@ -30,82 +39,82 @@ " \tmodel = \"Rainier\";\n" "@@ -351,66 +352,82 @@\n" " \n" - " \t\tgpio at 0 {\n" + " \t\tgpio@0 {\n" " \t\t\treg = <0>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" " \t\t};\n" " \n" - " \t\tgpio at 1 {\n" + " \t\tgpio@1 {\n" " \t\t\treg = <1>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" " \t\t};\n" " \n" - " \t\tgpio at 2 {\n" + " \t\tgpio@2 {\n" " \t\t\treg = <2>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" " \t\t};\n" " \n" - " \t\tgpio at 3 {\n" + " \t\tgpio@3 {\n" " \t\t\treg = <3>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" " \t\t};\n" " \n" - " \t\tgpio at 4 {\n" + " \t\tgpio@4 {\n" " \t\t\treg = <4>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" " \t\t};\n" " \n" - " \t\tgpio at 5 {\n" + " \t\tgpio@5 {\n" " \t\t\treg = <5>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" " \t\t};\n" " \n" - " \t\tgpio at 6 {\n" + " \t\tgpio@6 {\n" " \t\t\treg = <6>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" " \t\t};\n" " \n" - " \t\tgpio at 7 {\n" + " \t\tgpio@7 {\n" " \t\t\treg = <7>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" " \t\t};\n" " \n" - " \t\tgpio at 8 {\n" + " \t\tgpio@8 {\n" " \t\t\treg = <8>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" " \t\t};\n" " \n" - " \t\tgpio at 9 {\n" + " \t\tgpio@9 {\n" " \t\t\treg = <9>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" " \t\t};\n" " \n" - " \t\tgpio at 10 {\n" + " \t\tgpio@10 {\n" " \t\t\treg = <10>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" " \t\t};\n" " \n" - " \t\tgpio at 11 {\n" + " \t\tgpio@11 {\n" " \t\t\treg = <11>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" " \t\t};\n" " \n" - " \t\tgpio at 12 {\n" + " \t\tgpio@12 {\n" " \t\t\treg = <12>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" " \t\t};\n" " \n" - " \t\tgpio at 13 {\n" + " \t\tgpio@13 {\n" " \t\t\treg = <13>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" " \t\t};\n" " \n" - " \t\tgpio at 14 {\n" + " \t\tgpio@14 {\n" " \t\t\treg = <14>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" " \t\t};\n" " \n" - " \t\tgpio at 15 {\n" + " \t\tgpio@15 {\n" " \t\t\treg = <15>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" " \t\t};\n" @@ -114,4 +123,4 @@ "-- \n" 2.24.1 -ddddbd78d76a9f90ce646d1c64cb606ab1c175a2e00c9a45b3f4e3311de8af36 +6e65ab8db911ffa33f1c7b15a2bd8d70b8bfa7fe1b1400ef5b9d5389e53bd5d0
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