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[79.178.2.19]) by smtp.gmail.com with ESMTPSA id g4sm1533981qki.8.2020.03.09.20.32.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Mar 2020 20:32:10 -0700 (PDT) Date: Mon, 9 Mar 2020 23:32:05 -0400 From: "Michael S. Tsirkin" To: BALATON Zoltan Subject: Re: [PATCH v3 3/3] via-ide: Also emulate non 100% native mode Message-ID: <20200309232733-mutt-send-email-mst@kernel.org> References: <20200309163537-mutt-send-email-mst@kernel.org> MIME-Version: 1.0 In-Reply-To: X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-block@nongnu.org, philmd@redhat.com, Mark Cave-Ayland , qemu-devel@nongnu.org, Aleksandar Markovic , John Snow , Artyom Tarasenko , Richard Henderson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Mon, Mar 09, 2020 at 09:50:57PM +0100, BALATON Zoltan wrote: > On Mon, 9 Mar 2020, Michael S. Tsirkin wrote: > > On Mon, Mar 09, 2020 at 08:18:13PM +0100, BALATON Zoltan wrote: > > > Some machines operate in "non 100% native mode" where interrupts are > > > fixed at legacy IDE interrupts and some guests expect this behaviour > > > without checking based on knowledge about hardware. Even Linux has > > > arch specific workarounds for this that are activated on such boards > > > so this needs to be emulated as well. > > >=20 > > > Signed-off-by: BALATON Zoltan > > > --- > > > v2: Don't use PCI_INTERRUPT_LINE in via_ide_set_irq() > > > v3: Patch pci.c instead of local workaround for PCI reset clearing > > > PCI_INTERRUPT_PIN config reg > > >=20 > > > hw/ide/via.c | 37 +++++++++++++++++++++++++++++-------- > > > hw/mips/mips_fulong2e.c | 2 +- > > > include/hw/ide.h | 3 ++- > > > 3 files changed, 32 insertions(+), 10 deletions(-) > > >=20 > > > diff --git a/hw/ide/via.c b/hw/ide/via.c > > > index 096de8dba0..02d29809f2 100644 > > > --- a/hw/ide/via.c > > > +++ b/hw/ide/via.c > > > @@ -1,9 +1,10 @@ > > > /* > > > - * QEMU IDE Emulation: PCI VIA82C686B support. > > > + * QEMU VIA southbridge IDE emulation (VT82C686B, VT8231) > > > * > > > * Copyright (c) 2003 Fabrice Bellard > > > * Copyright (c) 2006 Openedhand Ltd. > > > * Copyright (c) 2010 Huacai Chen > > > + * Copyright (c) 2019-2020 BALATON Zoltan > > > * > > > * Permission is hereby granted, free of charge, to any person obtai= ning a copy > > > * of this software and associated documentation files (the "Softwar= e"), to deal > > > @@ -25,6 +26,8 @@ > > > */ > > >=20 > > > #include "qemu/osdep.h" > > > +#include "qemu/range.h" > > > +#include "hw/qdev-properties.h" > > > #include "hw/pci/pci.h" > > > #include "migration/vmstate.h" > > > #include "qemu/module.h" > > > @@ -111,11 +114,18 @@ static void via_ide_set_irq(void *opaque, int n= , int level) > > > } else { > > > d->config[0x70 + n * 8] &=3D ~0x80; > > > } > > > - > > > level =3D (d->config[0x70] & 0x80) || (d->config[0x78] & 0x80); > > > - n =3D pci_get_byte(d->config + PCI_INTERRUPT_LINE); > > > - if (n) { > > > - qemu_set_irq(isa_get_irq(NULL, n), level); > > > + > > > + /* > > > + * Some machines operate in "non 100% native mode" where PCI_INT= ERRUPT_LINE > > > + * is not used but IDE always uses ISA IRQ 14 and 15 even in nat= ive mode. > > > + * Some guest drivers expect this, often without checking. > > > + */ > > > + if (!(pci_get_byte(d->config + PCI_CLASS_PROG) & (n ? 4 : 1)) || > > > + PCI_IDE(d)->flags & BIT(PCI_IDE_LEGACY_IRQ)) { > > > + qemu_set_irq(isa_get_irq(NULL, (n ? 15 : 14)), level); > > > + } else { > > > + qemu_set_irq(isa_get_irq(NULL, 14), level); > > > } > > > } > > >=20 > > > @@ -169,7 +179,8 @@ static void via_ide_realize(PCIDevice *dev, Error= **errp) > > >=20 > > > pci_config_set_prog_interface(pci_conf, 0x8f); /* native PCI ATA= mode */ > > > pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); > > > - dev->wmask[PCI_INTERRUPT_LINE] =3D 0xf; > > > + dev->wmask[PCI_CLASS_PROG] =3D 5; > >=20 > > What's the story here? Why is class suddenly writeable? >=20 > The via-ide (function 1 of some VIA southbridge chips) use bits in this r= eg > to set legacy compatibility mode as described in VT82C686B and VT8231 > datasheets and Linux writes this on pegasos2 board I'm emulating. See lon= ger > description in this message: >=20 > https://lists.nongnu.org/archive/html/qemu-devel/2020-03/msg00019.html >=20 > Regards, > BALATON Zoltan Pls add a code comment so people don't have to dig through mailing list archives. --=20 MST