From: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
To: Florian Fainelli <f.fainelli@gmail.com>
Cc: Kamal Dasu <kdasu.kdev@gmail.com>,
linux-mips@vger.kernel.org,
bcm-kernel-feedback-list@broadcom.com,
Ralf Baechle <ralf@linux-mips.org>,
Paul Burton <paulburton@kernel.org>,
James Hogan <jhogan@kernel.org>,
Jiaxun Yang <jiaxun.yang@flygoat.com>,
Huacai Chen <chenhc@lemote.com>,
Mike Rapoport <rppt@linux.ibm.com>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2] MIPS: c-r4k: Invalidate BMIPS5000 ZSCM prefetch lines
Date: Wed, 11 Mar 2020 22:44:32 +0100 [thread overview]
Message-ID: <20200311214432.GA5900@alpha.franken.de> (raw)
In-Reply-To: <53c0ca2d-84a5-7556-c1f4-a75e99f0a743@gmail.com>
On Wed, Mar 11, 2020 at 01:54:23PM -0700, Florian Fainelli wrote:
> On 2/7/20 2:33 PM, Kamal Dasu wrote:
> > Zephyr secondary cache is 256KB, 128B lines. 32B sectors. A secondary cache
> > line can contain two instruction cache lines (64B), or four data cache
> > lines (32B). Hardware prefetch Cache detects stream access, and prefetches
> > ahead of processor access. Add support to invalidate BMIPS5000 cpu zephyr
> > secondary cache module (ZSCM) on DMA from device so that data returned is
> > coherent during DMA read operations.
> >
> > Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
>
> Thomas can review and apply this patch? Thank you!
looks good to me. I only wonder whether r4k_dma_cache_wbinv() also
needs this ?
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
next prev parent reply other threads:[~2020-03-11 21:44 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-07 22:33 [PATCH v2] MIPS: c-r4k: Invalidate BMIPS5000 ZSCM prefetch lines Kamal Dasu
2020-02-07 22:35 ` Florian Fainelli
2020-03-11 20:54 ` Florian Fainelli
2020-03-11 21:44 ` Thomas Bogendoerfer [this message]
2020-03-13 3:09 ` Kamal Dasu
2020-03-16 15:31 ` Thomas Bogendoerfer
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