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Peter Anvin" , Jiri Olsa , Mark Rutland , Michael Petlan , Namhyung Kim , Stephane Eranian , linux-kernel@vger.kernel.org, x86@kernel.org Subject: [PATCH 3/3 v2] perf/amd/uncore: Add support for Family 19h L3 PMU Date: Fri, 13 Mar 2020 18:10:24 -0500 Message-Id: <20200313231024.17601-3-kim.phillips@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200313231024.17601-1-kim.phillips@amd.com> References: <20200313231024.17601-1-kim.phillips@amd.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: DM3PR08CA0013.namprd08.prod.outlook.com (2603:10b6:0:52::23) To SN6PR12MB2845.namprd12.prod.outlook.com (2603:10b6:805:75::33) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from fritz.amd.com (165.204.77.1) by DM3PR08CA0013.namprd08.prod.outlook.com (2603:10b6:0:52::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2793.17 via Frontend Transport; Fri, 13 Mar 2020 23:11:00 +0000 X-Mailer: git-send-email 2.25.1 X-Originating-IP: [165.204.77.1] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: ca667cde-c73c-4a3b-1111-08d7c7a3cc24 X-MS-TrafficTypeDiagnostic: SN6PR12MB2846:|SN6PR12MB2846: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1332; X-Forefront-PRVS: 034119E4F6 X-Forefront-Antispam-Report: SFV:NSPM;SFS:(10009020)(4636009)(366004)(39860400002)(376002)(136003)(396003)(346002)(199004)(81166006)(81156014)(86362001)(110136005)(6666004)(316002)(7049001)(966005)(186003)(52116002)(66946007)(36756003)(66556008)(54906003)(66476007)(7696005)(4326008)(1076003)(44832011)(2906002)(5660300002)(26005)(2616005)(956004)(8676002)(16526019)(478600001)(8936002)(6486002)(7416002);DIR:OUT;SFP:1101;SCL:1;SRVR:SN6PR12MB2846;H:SN6PR12MB2845.namprd12.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1; Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: mlZUv/9/oAbiYp0/EUd7U6kfw2Nyi1EKXWRRrHEbKSttbBgxZxnkPQ1OJvYV8jm/Ux/TZ/YONOvDkdlZEMRnkMgtbSNdZwUXO+3c+FcRWzBs4UstiUKWK32hM/6bsU+IsVILm5J0HsR61nMi7MaCcsBSHj+kBE6irOXFK7ke04f8Po4SC0RU6qaWFzdc88k7KBdu81wuAh73S64M0uo7dVtpV7OQRNBhBLlPytla/HTgLqxEkzCgR9RRFdEzA1SpVOY4dyOUiyviwzJlXaYneqhlsyFBH6K0zzjIYM93oY5aEr/qaxbJ8IBInhAP91I3eJO9iE7TUMr2WIqWTv8zMLpIRuQYwoTdjvRHBQht2LicZww/uhhkl7hIEx/u7d69JVogyJ3crBWM6LM7agODUYqFrz+SS9GNcUnkuUANKlJp1fYy9sybFmdaOuCCTm2cdWGxOFhtoj5otdqCKiJ0jJdvfv+BDEG1k6oWepXgpcYQxSTjvrlrrETIamgVekK4kD4ue4vBOhhi8BuDeLlTRw== X-MS-Exchange-AntiSpam-MessageData: z/AqCj/kSA5LU49Pwwi6qnjVXoQQ17zusymdFEo+jHxaiWWt/pMe/8mF03bUfAQRD3gG+c/bKiZrkrzmPsyrgaK4cisxDly9RJEh4I/xID9cmKFqpTCHcI8sCRap/PtDNBTk9fnDcj/yZl+8r5ylhw== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: ca667cde-c73c-4a3b-1111-08d7c7a3cc24 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Mar 2020 23:11:01.6678 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: ONqwDEUNM1vC46DdTGPWloZgCArI3VhkDmjR0Bh58dowZE1SU75+9ioQmsSMo9GhAlAlJmKPN+ug4xjuo4LjbA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2846 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Family 19h introduces change in slice, core and thread specification in its L3 Performance Event Select (ChL3PmcCfg) h/w register. The change is incompatible with Family 17h's version of the register. Introduce a new path in l3_thread_slice_mask() do things differently for Family 19h vs. Family 17h, otherwise the new hardware doesn't get programmed correctly. Instead of a linear core--thread bitmask, Family 19h takes an encoded core number, and a separate thread mask. There are new bits that are set for all cores and all slices, of which only the latter is used, since the driver counts events for all slices on behalf of the specified cpu. Also update amd_uncore_init() to base its L2/NB vs. L3/Data Fabric mode decision based on Family 17h or above, not just 17h and 18h: the Family 19h Data Fabric PMC is compatible with the Family 17h DF PMC. Signed-off-by: Kim Phillips Cc: Alexander Shishkin Cc: Arnaldo Carvalho de Melo Cc: Borislav Petkov Cc: "H. Peter Anvin" Cc: Ingo Molnar Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Michael Petlan Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Stephane Eranian Cc: Thomas Gleixner Cc: linux-kernel@vger.kernel.org Cc: x86@kernel.org --- v2: rewrote commit text to not use "We" etc., based on Boris' comments: https://lkml.org/lkml/2020/3/12/583 arch/x86/events/amd/uncore.c | 20 ++++++++++++++------ arch/x86/include/asm/perf_event.h | 15 +++++++++++++-- 2 files changed, 27 insertions(+), 8 deletions(-) diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c index b622e59ccdd0..f3d5e4e2f285 100644 --- a/arch/x86/events/amd/uncore.c +++ b/arch/x86/events/amd/uncore.c @@ -191,10 +191,18 @@ static u64 l3_thread_slice_mask(int cpu) if (topology_smt_supported() && !topology_is_primary_thread(cpu)) thread = 1; - shift = AMD64_L3_THREAD_SHIFT + 2 * (core % 4) + thread; + if (boot_cpu_data.x86 <= 0x18) { + shift = AMD64_L3_THREAD_SHIFT + 2 * (core % 4) + thread; + thread_mask = BIT_ULL(shift); + + return AMD64_L3_SLICE_MASK | thread_mask; + } + + core = (core << AMD64_L3_COREID_SHIFT) & AMD64_L3_COREID_MASK; + shift = AMD64_L3_THREAD_SHIFT + thread; thread_mask = BIT_ULL(shift); - return AMD64_L3_SLICE_MASK | thread_mask; + return AMD64_L3_EN_ALL_SLICES | core | thread_mask; } static int amd_uncore_event_init(struct perf_event *event) @@ -223,8 +231,8 @@ static int amd_uncore_event_init(struct perf_event *event) return -EINVAL; /* - * SliceMask and ThreadMask need to be set for certain L3 events in - * Family 17h. For other events, the two fields do not affect the count. + * SliceMask and ThreadMask need to be set for certain L3 events. + * For other events, the two fields do not affect the count. */ if (l3_mask && is_llc_event(event)) hwc->config |= l3_thread_slice_mask(event->cpu); @@ -533,9 +541,9 @@ static int __init amd_uncore_init(void) if (!boot_cpu_has(X86_FEATURE_TOPOEXT)) return -ENODEV; - if (boot_cpu_data.x86 == 0x17 || boot_cpu_data.x86 == 0x18) { + if (boot_cpu_data.x86 >= 0x17) { /* - * For F17h or F18h, the Northbridge counters are + * For F17h and above, the Northbridge counters are * repurposed as Data Fabric counters. Also, L3 * counters are supported too. The PMUs are exported * based on family as either L2 or L3 and NB or DF. diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h index 29964b0e1075..e855e9cf2c37 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -50,11 +50,22 @@ #define AMD64_L3_SLICE_SHIFT 48 #define AMD64_L3_SLICE_MASK \ - ((0xFULL) << AMD64_L3_SLICE_SHIFT) + (0xFULL << AMD64_L3_SLICE_SHIFT) +#define AMD64_L3_SLICEID_MASK \ + (0x7ULL << AMD64_L3_SLICE_SHIFT) #define AMD64_L3_THREAD_SHIFT 56 #define AMD64_L3_THREAD_MASK \ - ((0xFFULL) << AMD64_L3_THREAD_SHIFT) + (0xFFULL << AMD64_L3_THREAD_SHIFT) +#define AMD64_L3_F19H_THREAD_MASK \ + (0x3ULL << AMD64_L3_THREAD_SHIFT) + +#define AMD64_L3_EN_ALL_CORES BIT_ULL(47) +#define AMD64_L3_EN_ALL_SLICES BIT_ULL(46) + +#define AMD64_L3_COREID_SHIFT 42 +#define AMD64_L3_COREID_MASK \ + (0x7ULL << AMD64_L3_COREID_SHIFT) #define X86_RAW_EVENT_MASK \ (ARCH_PERFMON_EVENTSEL_EVENT | \ -- 2.25.1