[char-misc:char-misc-testing 39/83] drivers/mmc/host/sdhci-of-arasan.c:668: undefined reference to `zynqmp_pm_set_sd_tapdelay'

[kbuild test robot <lkp@intel.com>]

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tree:   https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc.git char-misc-testing
head:   3a371debecc5a16e2f9c0d9de6ffc75c17f7e88b
commit: 04c11b3697c64974301ad375f7a2953ee4f4a11a [39/83] firmware: xilinx: Use APIs instead of IOCTLs
config: arm-randconfig-a001-20200318 (attached as .config)
compiler: arm-linux-gnueabi-gcc (GCC) 9.2.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        git checkout 04c11b3697c64974301ad375f7a2953ee4f4a11a
        # save the attached .config to linux build tree
        GCC_VERSION=9.2.0 make.cross ARCH=arm 

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

   arm-linux-gnueabi-ld: drivers/mmc/host/sdhci-of-arasan.o: in function `sdhci_zynqmp_sdcardclk_set_phase':
>> drivers/mmc/host/sdhci-of-arasan.c:668: undefined reference to `zynqmp_pm_set_sd_tapdelay'
   arm-linux-gnueabi-ld: drivers/mmc/host/sdhci-of-arasan.o: in function `sdhci_zynqmp_sampleclk_set_phase':
   drivers/mmc/host/sdhci-of-arasan.c:736: undefined reference to `zynqmp_pm_set_sd_tapdelay'

vim +668 drivers/mmc/host/sdhci-of-arasan.c

   622	
   623	{
   624		struct sdhci_arasan_clk_data *clk_data =
   625			container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw);
   626		struct sdhci_arasan_data *sdhci_arasan =
   627			container_of(clk_data, struct sdhci_arasan_data, clk_data);
   628		struct sdhci_host *host = sdhci_arasan->host;
   629		const char *clk_name = clk_hw_get_name(hw);
   630		u32 node_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 : NODE_SD_1;
   631		u8 tap_delay, tap_max = 0;
   632		int ret;
   633	
   634		/*
   635		 * This is applicable for SDHCI_SPEC_300 and above
   636		 * ZynqMP does not set phase for <=25MHz clock.
   637		 * If degrees is zero, no need to do anything.
   638		 */
   639		if (host->version < SDHCI_SPEC_300 ||
   640		    host->timing == MMC_TIMING_LEGACY ||
   641		    host->timing == MMC_TIMING_UHS_SDR12 || !degrees)
   642			return 0;
   643	
   644		switch (host->timing) {
   645		case MMC_TIMING_MMC_HS:
   646		case MMC_TIMING_SD_HS:
   647		case MMC_TIMING_UHS_SDR25:
   648		case MMC_TIMING_UHS_DDR50:
   649		case MMC_TIMING_MMC_DDR52:
   650			/* For 50MHz clock, 30 Taps are available */
   651			tap_max = 30;
   652			break;
   653		case MMC_TIMING_UHS_SDR50:
   654			/* For 100MHz clock, 15 Taps are available */
   655			tap_max = 15;
   656			break;
   657		case MMC_TIMING_UHS_SDR104:
   658		case MMC_TIMING_MMC_HS200:
   659			/* For 200MHz clock, 8 Taps are available */
   660			tap_max = 8;
   661		default:
   662			break;
   663		}
   664	
   665		tap_delay = (degrees * tap_max) / 360;
   666	
   667		/* Set the Clock Phase */
 > 668		ret = zynqmp_pm_set_sd_tapdelay(node_id, PM_TAPDELAY_OUTPUT, tap_delay);
   669		if (ret)
   670			pr_err("Error setting Output Tap Delay\n");
   671	
   672		return ret;
   673	}
   674	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org

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