From: Segher Boessenkool <segher@kernel.crashing.org>
To: "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com>
Cc: linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH] arch/powerpc/64: Avoid isync in flush_dcache_range
Date: Fri, 20 Mar 2020 10:05:39 -0500 [thread overview]
Message-ID: <20200320150539.GF22482@gate.crashing.org> (raw)
In-Reply-To: <20200320103242.229223-1-aneesh.kumar@linux.ibm.com>
On Fri, Mar 20, 2020 at 04:02:42PM +0530, Aneesh Kumar K.V wrote:
> As per ISA and isync is only needed on instruction cache
> block invalidate. Remove the same from dcache invalidate.
Is that true on older CPUs?
Segher
next prev parent reply other threads:[~2020-03-20 15:09 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-20 10:32 [PATCH] arch/powerpc/64: Avoid isync in flush_dcache_range Aneesh Kumar K.V
2020-03-20 15:05 ` Segher Boessenkool [this message]
2020-03-20 15:08 ` Aneesh Kumar K.V
2020-03-20 15:27 ` Segher Boessenkool
2020-04-01 12:53 ` Michael Ellerman
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