[PATCH 1/6] Add BCM2835 SOC MPHI emulation

[Paul Zimmerman <pauldzim@gmail.com>]

Add BCM2835 SOC MPHI emulation. It is very basic, only providing
the FIQ interrupt needed to allow the dwc-otg USB host controller
driver in the Raspbian kernel to function.

Signed-off-by: Paul Zimmerman <pauldzim@gmail.com>
---
 hw/arm/bcm2835_peripherals.c         |  17 +++
 hw/misc/Makefile.objs                |   1 +
 hw/misc/bcm2835_mphi.c               | 215 +++++++++++++++++++++++++++
 include/hw/arm/bcm2835_peripherals.h |   2 +
 include/hw/misc/bcm2835_mphi.h       |  50 +++++++
 5 files changed, 285 insertions(+)
 create mode 100644 hw/misc/bcm2835_mphi.c
 create mode 100644 include/hw/misc/bcm2835_mphi.h

diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
index 17207ae07e..dd7e6883cb 100644
--- a/hw/arm/bcm2835_peripherals.c
+++ b/hw/arm/bcm2835_peripherals.c
@@ -123,6 +123,10 @@ static void bcm2835_peripherals_init(Object *obj)
     sysbus_init_child_obj(obj, "gpio", &s->gpio, sizeof(s->gpio),
                           TYPE_BCM2835_GPIO);
 
+    /* Mphi */
+    sysbus_init_child_obj(obj, "mphi", &s->mphi, sizeof(s->mphi),
+                          TYPE_BCM2835_MPHI);
+
     object_property_add_const_link(OBJECT(&s->gpio), "sdbus-sdhci",
                                    OBJECT(&s->sdhci.sdbus), &error_abort);
     object_property_add_const_link(OBJECT(&s->gpio), "sdbus-sdhost",
@@ -367,6 +371,19 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
         return;
     }
 
+    /* Mphi */
+    object_property_set_bool(OBJECT(&s->mphi), true, "realized", &err);
+    if (err) {
+        error_propagate(errp, err);
+        return;
+    }
+
+    memory_region_add_subregion(&s->peri_mr, MPHI_OFFSET,
+                sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mphi), 0));
+    sysbus_connect_irq(SYS_BUS_DEVICE(&s->mphi), 0,
+        qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
+                               INTERRUPT_HOSTPORT));
+
     create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);
     create_unimp(s, &s->cprman, "bcm2835-cprman", CPRMAN_OFFSET, 0x1000);
     create_unimp(s, &s->a2w, "bcm2835-a2w", A2W_OFFSET, 0x1000);
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index 68aae2eabb..91085cc21b 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -57,6 +57,7 @@ common-obj-$(CONFIG_OMAP) += omap_l4.o
 common-obj-$(CONFIG_OMAP) += omap_sdrc.o
 common-obj-$(CONFIG_OMAP) += omap_tap.o
 common-obj-$(CONFIG_RASPI) += bcm2835_mbox.o
+common-obj-$(CONFIG_RASPI) += bcm2835_mphi.o
 common-obj-$(CONFIG_RASPI) += bcm2835_property.o
 common-obj-$(CONFIG_RASPI) += bcm2835_rng.o
 common-obj-$(CONFIG_RASPI) += bcm2835_thermal.o
diff --git a/hw/misc/bcm2835_mphi.c b/hw/misc/bcm2835_mphi.c
new file mode 100644
index 0000000000..32433ce156
--- /dev/null
+++ b/hw/misc/bcm2835_mphi.c
@@ -0,0 +1,215 @@
+/*
+ * BCM2835 SOC MPHI emulation
+ *
+ * Very basic emulation, only providing the FIQ interrupt needed to
+ * allow the dwc-otg USB host controller driver in the Raspbian kernel
+ * to function.
+ *
+ * Copyright (c) 2020 Paul Zimmerman <pauldzim@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/misc/bcm2835_mphi.h"
+#include "qemu/error-report.h"
+#include "qemu/main-loop.h"
+
+//#define MPHI_DEBUG      1
+
+#ifdef MPHI_DEBUG
+#define DPRINTF(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__)
+#else
+#define DPRINTF(fmt, ...) do {} while(0)
+#endif
+
+static inline void mphi_raise_irq(BCM2835MphiState *s)
+{
+    DPRINTF("mphi_raise_irq, s %p\n", s);
+    qemu_set_irq(s->irq, 1);
+}
+
+static inline void mphi_lower_irq(BCM2835MphiState *s)
+{
+    DPRINTF("mphi_lower_irq, s %p\n", s);
+    qemu_set_irq(s->irq, 0);
+}
+
+static uint64_t mphi_reg_read(void *ptr, hwaddr addr, unsigned size)
+{
+    BCM2835MphiState *s = ptr;
+    uint32_t reg = s->regbase + addr;
+    uint32_t val = 0;
+
+    switch (reg) {
+    case 0x28:  /* outdda */
+        val = s->outdda;
+        break;
+    case 0x2c:  /* outddb */
+        val = s->outddb;
+        break;
+    case 0x4c:  /* ctrl */
+        val = s->ctrl;
+        val |= 1 << 17;
+        break;
+    case 0x50:  /* intstat */
+        val = s->intstat;
+        break;
+    case 0x1f0: /* swirq_set */
+        val = s->swirq_set;
+        break;
+    case 0x1f4: /* swirq_clr */
+        val = s->swirq_clr;
+        break;
+    default:
+        break;
+    }
+
+    DPRINTF("mphi_reg_read   0x%04lx val 0x%08x\n", addr, val);
+    return val;
+}
+
+static void mphi_reg_write(void *ptr, hwaddr addr, uint64_t val, unsigned size)
+{
+    BCM2835MphiState *s = ptr;
+    uint32_t reg = s->regbase + addr;
+    uint32_t old;
+    int do_irq = 0;
+
+    DPRINTF("mphi_reg_write  0x%04lx val 0x%08lx ", addr, val);
+    val &= 0xffffffff;
+
+    switch (reg) {
+    case 0x28:  /* outdda */
+        old = s->outdda;
+        s->outdda = val;
+        break;
+    case 0x2c:  /* outddb */
+        old = s->outddb;
+        s->outddb = val;
+        if (val & (1 << 29))
+            do_irq = 1;
+        break;
+    case 0x4c:  /* ctrl */
+        old = s->ctrl;
+        s->ctrl = val;
+        if (val & (1 << 16))
+            do_irq = -1;
+        break;
+    case 0x50:  /* intstat */
+        old = s->intstat;
+        s->intstat = val;
+        if (val & ((1 << 16) | (1 << 29)))
+            do_irq = -1;
+        break;
+    case 0x1f0: /* swirq_set */
+        old = s->swirq_set;
+        s->swirq_set = val;
+        do_irq = 1;
+        break;
+    case 0x1f4: /* swirq_clr */
+        old = s->swirq_clr;
+        s->swirq_clr = val;
+        do_irq = -1;
+        break;
+    default:
+        break;
+    }
+
+    DPRINTF("old 0x%08x result 0x%08lx\n", old, val);
+    old = old;
+    if (do_irq > 0)
+        mphi_raise_irq(s);
+    else if (do_irq < 0)
+        mphi_lower_irq(s);
+}
+
+static const MemoryRegionOps mphi_mmio_ops = {
+    .read = mphi_reg_read,
+    .write = mphi_reg_write,
+    .valid.min_access_size = 4,
+    .valid.max_access_size = 4,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static void mphi_realize(BCM2835MphiState *s, DeviceState *dev, Error **errp)
+{
+    DPRINTF("mphi_realize, s %p dev %p\n", s, dev);
+    s->device = dev;
+}
+
+static void mphi_init(BCM2835MphiState *s, DeviceState *dev)
+{
+    DPRINTF("usb_mphi_init, s %p dev %p\n", s, dev);
+
+    memory_region_init(&s->mem, OBJECT(dev), "mphi", MPHI_MMIO_SIZE);
+    memory_region_init_io(&s->mem_reg, OBJECT(dev), &mphi_mmio_ops, s,
+                          "global", 0x200);
+    memory_region_add_subregion(&s->mem, s->regbase, &s->mem_reg);
+}
+
+static void mphi_sysbus_reset(DeviceState *dev)
+{
+#ifdef MPHI_DEBUG
+    SysBusDevice *d = SYS_BUS_DEVICE(dev);
+    BCM2835MphiState *s = BCM2835_MPHI(d);
+#endif
+
+    DPRINTF("mphi_sysbus_reset, dev %p d %p s %p\n", dev, d, s);
+}
+
+static void mphi_sysbus_realize(DeviceState *dev, Error **errp)
+{
+    SysBusDevice *d = SYS_BUS_DEVICE(dev);
+    BCM2835MphiState *s = BCM2835_MPHI(dev);
+
+    DPRINTF("mphi_sysbus_realize, dev %p d %p s %p\n", dev, d, s);
+    mphi_realize(s, dev, errp);
+    sysbus_init_irq(d, &s->irq);
+}
+
+static void mphi_sysbus_init(Object *obj)
+{
+    SysBusDevice *d = SYS_BUS_DEVICE(obj);
+    BCM2835MphiState *s = BCM2835_MPHI(obj);
+
+    DPRINTF("mphi_sysbus_init, obj %p d %p s %p\n", obj, d, s);
+    s->regbase = 0;
+    s->as = &address_space_memory;
+    mphi_init(s, DEVICE(obj));
+    sysbus_init_mmio(d, &s->mem);
+}
+
+static void mphi_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    DPRINTF("mphi_class_init, class %p dc %p\n", klass, dc);
+    dc->realize = mphi_sysbus_realize;
+    dc->reset = mphi_sysbus_reset;
+}
+
+static const TypeInfo bcm2835_mphi_type_info = {
+     .name          = TYPE_BCM2835_MPHI,
+     .parent        = TYPE_SYS_BUS_DEVICE,
+     .instance_size = sizeof(BCM2835MphiState),
+     .instance_init = mphi_sysbus_init,
+     .class_init    = mphi_class_init,
+};
+
+static void bcm2835_mphi_register_types(void)
+{
+    DPRINTF("bcm2835_mphi_register_types\n");
+    type_register_static(&bcm2835_mphi_type_info);
+}
+
+type_init(bcm2835_mphi_register_types)
diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
index 7859281e11..77958ca60e 100644
--- a/include/hw/arm/bcm2835_peripherals.h
+++ b/include/hw/arm/bcm2835_peripherals.h
@@ -20,6 +20,7 @@
 #include "hw/misc/bcm2835_property.h"
 #include "hw/misc/bcm2835_rng.h"
 #include "hw/misc/bcm2835_mbox.h"
+#include "hw/misc/bcm2835_mphi.h"
 #include "hw/misc/bcm2835_thermal.h"
 #include "hw/sd/sdhci.h"
 #include "hw/sd/bcm2835_sdhost.h"
@@ -41,6 +42,7 @@ typedef struct BCM2835PeripheralState {
     qemu_irq irq, fiq;
 
     BCM2835SystemTimerState systmr;
+    BCM2835MphiState mphi;
     UnimplementedDeviceState armtmr;
     UnimplementedDeviceState cprman;
     UnimplementedDeviceState a2w;
diff --git a/include/hw/misc/bcm2835_mphi.h b/include/hw/misc/bcm2835_mphi.h
new file mode 100644
index 0000000000..826ae2af3b
--- /dev/null
+++ b/include/hw/misc/bcm2835_mphi.h
@@ -0,0 +1,50 @@
+/*
+ * BCM2835 SOC MPHI state definitions
+ *
+ * Copyright (c) 2020 Paul Zimmerman <pauldzim@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef HW_MISC_BCM2835_MPHI_H
+#define HW_MISC_BCM2835_MPHI_H
+
+#include "hw/irq.h"
+#include "hw/sysbus.h"
+#include "sysemu/dma.h"
+
+#define MPHI_MMIO_SIZE      0x1000
+
+typedef struct BCM2835MphiState BCM2835MphiState;
+
+struct BCM2835MphiState {
+    SysBusDevice parent_obj;
+    DeviceState *device;
+    qemu_irq irq;
+    AddressSpace *as;
+    MemoryRegion mem;
+    MemoryRegion mem_reg;
+    uint16_t regbase;
+
+    uint32_t outdda;
+    uint32_t outddb;
+    uint32_t ctrl;
+    uint32_t intstat;
+    uint32_t swirq_set;
+    uint32_t swirq_clr;
+};
+
+#define TYPE_BCM2835_MPHI   "bcm2835-mphi"
+
+#define BCM2835_MPHI(obj) \
+    OBJECT_CHECK(BCM2835MphiState, (obj), TYPE_BCM2835_MPHI)
+
+#endif
-- 
2.17.1