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[91.78.208.152]) by smtp.gmail.com with ESMTPSA id f23sm2449005lja.60.2020.03.29.18.09.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Mar 2020 18:09:33 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?UTF-8?q?Artur=20=C5=9Awigo=C5=84?= , Georgi Djakov , Rob Herring Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v2 00/22] Introduce memory interconnect for NVIDIA Tegra SoCs Date: Mon, 30 Mar 2020 04:08:42 +0300 Message-Id: <20200330010904.27643-1-digetx@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Hello, This series brings initial support for memory interconnect to Tegra20 and Tegra30 SoCs. The interconnect provides are quite generic and should be suitable for all Tegra SoCs, but currently support is added only for these two generations of Tegra SoCs. For the starter only display controllers are getting interconnect API support, others could be supported later on. The display controllers have the biggest demand for interconnect API right now because dynamic memory frequency scaling can't be done safely without taking into account bandwidth requirement from the displays. (!) Please note that the EMC patches are made on top of the other EMC patches [1][2] that I was sending out recently. [1] https://patchwork.ozlabs.org/project/linux-tegra/list/?series=164165 [2] https://patchwork.ozlabs.org/project/linux-tegra/list/?series=165451 Changelog: v2: - Instead of a single dma-mem interconnect path, the paths are now defined per memory client. - The EMC provider now uses #interconnect-cells=<0>. - Dropped Tegra124 because there is no enough information about how to properly calculate required EMC clock rate for it and I don't have hardware for testing. Somebody else will have to work on it. - Moved interconnect providers code into drivers/memory/tegra/*. - Added "Create tegra20-devfreq device" patch because interconnect is not very usable without the devfreq memory auto-scaling since memory freq will be fixed to the display's requirement. Artur Świgoń (1): interconnect: Relax requirement in of_icc_get_from_provider() Dmitry Osipenko (21): dt-bindings: memory: tegra20: mc: Document new interconnect property dt-bindings: memory: tegra20: emc: Document new interconnect property dt-bindings: memory: tegra30: mc: Document new interconnect property dt-bindings: memory: tegra30: emc: Document new interconnect property dt-bindings: host1x: Document new interconnect properties dt-bindings: memory: tegra20: Add memory client IDs dt-bindings: memory: tegra30: Add memory client IDs ARM: tegra: Add interconnect properties to Tegra20 device-tree ARM: tegra: Add interconnect properties to Tegra30 device-tree memory: tegra: Register as interconnect provider memory: tegra20-emc: Use devm_platform_ioremap_resource memory: tegra20-emc: Continue probing if timings are missing in device-tree memory: tegra20-emc: Register as interconnect provider memory: tegra20-emc: Create tegra20-devfreq device memory: tegra30-emc: Continue probing if timings are missing in device-tree memory: tegra30-emc: Register as interconnect provider drm/tegra: dc: Support memory bandwidth management drm/tegra: dc: Tune up high priority request controls for Tegra20 drm/tegra: dc: Extend debug stats with total number of events ARM: tegra: Enable interconnect API in tegra_defconfig ARM: multi_v7_defconfig: Enable interconnect API .../display/tegra/nvidia,tegra20-host1x.txt | 68 +++++ .../memory-controllers/nvidia,tegra20-emc.txt | 2 + .../memory-controllers/nvidia,tegra20-mc.txt | 3 + .../nvidia,tegra30-emc.yaml | 6 + .../memory-controllers/nvidia,tegra30-mc.yaml | 5 + arch/arm/boot/dts/tegra20.dtsi | 22 +- arch/arm/boot/dts/tegra30.dtsi | 23 +- arch/arm/configs/multi_v7_defconfig | 1 + arch/arm/configs/tegra_defconfig | 1 + drivers/gpu/drm/tegra/dc.c | 289 +++++++++++++++++- drivers/gpu/drm/tegra/dc.h | 13 + drivers/gpu/drm/tegra/drm.c | 19 ++ drivers/gpu/drm/tegra/plane.c | 1 + drivers/gpu/drm/tegra/plane.h | 4 +- drivers/interconnect/core.c | 11 +- drivers/memory/tegra/mc.c | 118 +++++++ drivers/memory/tegra/mc.h | 8 + drivers/memory/tegra/tegra20-emc.c | 161 ++++++++-- drivers/memory/tegra/tegra30-emc.c | 144 ++++++++- include/dt-bindings/memory/tegra20-mc.h | 53 ++++ include/dt-bindings/memory/tegra30-mc.h | 67 ++++ include/soc/tegra/mc.h | 3 + 22 files changed, 975 insertions(+), 47 deletions(-) -- 2.25.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dmitry Osipenko Subject: [PATCH v2 00/22] Introduce memory interconnect for NVIDIA Tegra SoCs Date: Mon, 30 Mar 2020 04:08:42 +0300 Message-ID: <20200330010904.27643-1-digetx@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Return-path: Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Thierry Reding , Jonathan Hunter , =?UTF-8?q?Artur=20=C5=9Awigo=C5=84?= , Georgi Djakov , Rob Herring Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: linux-tegra@vger.kernel.org Hello, This series brings initial support for memory interconnect to Tegra20 and Tegra30 SoCs. The interconnect provides are quite generic and should be suitable for all Tegra SoCs, but currently support is added only for these two generations of Tegra SoCs. For the starter only display controllers are getting interconnect API support, others could be supported later on. The display controllers have the biggest demand for interconnect API right now because dynamic memory frequency scaling can't be done safely without taking into account bandwidth requirement from the displays. (!) Please note that the EMC patches are made on top of the other EMC patches [1][2] that I was sending out recently. [1] https://patchwork.ozlabs.org/project/linux-tegra/list/?series=164165 [2] https://patchwork.ozlabs.org/project/linux-tegra/list/?series=165451 Changelog: v2: - Instead of a single dma-mem interconnect path, the paths are now defined per memory client. - The EMC provider now uses #interconnect-cells=<0>. - Dropped Tegra124 because there is no enough information about how to properly calculate required EMC clock rate for it and I don't have hardware for testing. Somebody else will have to work on it. - Moved interconnect providers code into drivers/memory/tegra/*. - Added "Create tegra20-devfreq device" patch because interconnect is not very usable without the devfreq memory auto-scaling since memory freq will be fixed to the display's requirement. Artur Świgoń (1): interconnect: Relax requirement in of_icc_get_from_provider() Dmitry Osipenko (21): dt-bindings: memory: tegra20: mc: Document new interconnect property dt-bindings: memory: tegra20: emc: Document new interconnect property dt-bindings: memory: tegra30: mc: Document new interconnect property dt-bindings: memory: tegra30: emc: Document new interconnect property dt-bindings: host1x: Document new interconnect properties dt-bindings: memory: tegra20: Add memory client IDs dt-bindings: memory: tegra30: Add memory client IDs ARM: tegra: Add interconnect properties to Tegra20 device-tree ARM: tegra: Add interconnect properties to Tegra30 device-tree memory: tegra: Register as interconnect provider memory: tegra20-emc: Use devm_platform_ioremap_resource memory: tegra20-emc: Continue probing if timings are missing in device-tree memory: tegra20-emc: Register as interconnect provider memory: tegra20-emc: Create tegra20-devfreq device memory: tegra30-emc: Continue probing if timings are missing in device-tree memory: tegra30-emc: Register as interconnect provider drm/tegra: dc: Support memory bandwidth management drm/tegra: dc: Tune up high priority request controls for Tegra20 drm/tegra: dc: Extend debug stats with total number of events ARM: tegra: Enable interconnect API in tegra_defconfig ARM: multi_v7_defconfig: Enable interconnect API .../display/tegra/nvidia,tegra20-host1x.txt | 68 +++++ .../memory-controllers/nvidia,tegra20-emc.txt | 2 + .../memory-controllers/nvidia,tegra20-mc.txt | 3 + .../nvidia,tegra30-emc.yaml | 6 + .../memory-controllers/nvidia,tegra30-mc.yaml | 5 + arch/arm/boot/dts/tegra20.dtsi | 22 +- arch/arm/boot/dts/tegra30.dtsi | 23 +- arch/arm/configs/multi_v7_defconfig | 1 + arch/arm/configs/tegra_defconfig | 1 + drivers/gpu/drm/tegra/dc.c | 289 +++++++++++++++++- drivers/gpu/drm/tegra/dc.h | 13 + drivers/gpu/drm/tegra/drm.c | 19 ++ drivers/gpu/drm/tegra/plane.c | 1 + drivers/gpu/drm/tegra/plane.h | 4 +- drivers/interconnect/core.c | 11 +- drivers/memory/tegra/mc.c | 118 +++++++ drivers/memory/tegra/mc.h | 8 + drivers/memory/tegra/tegra20-emc.c | 161 ++++++++-- drivers/memory/tegra/tegra30-emc.c | 144 ++++++++- include/dt-bindings/memory/tegra20-mc.h | 53 ++++ include/dt-bindings/memory/tegra30-mc.h | 67 ++++ include/soc/tegra/mc.h | 3 + 22 files changed, 975 insertions(+), 47 deletions(-) -- 2.25.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.3 required=3.0 tests=DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD171C43331 for ; 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[91.78.208.152]) by smtp.gmail.com with ESMTPSA id f23sm2449005lja.60.2020.03.29.18.09.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Mar 2020 18:09:33 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?UTF-8?q?Artur=20=C5=9Awigo=C5=84?= , Georgi Djakov , Rob Herring Subject: [PATCH v2 00/22] Introduce memory interconnect for NVIDIA Tegra SoCs Date: Mon, 30 Mar 2020 04:08:42 +0300 Message-Id: <20200330010904.27643-1-digetx@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Mailman-Approved-At: Mon, 30 Mar 2020 07:11:44 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" SGVsbG8sCgpUaGlzIHNlcmllcyBicmluZ3MgaW5pdGlhbCBzdXBwb3J0IGZvciBtZW1vcnkgaW50 ZXJjb25uZWN0IHRvIFRlZ3JhMjAgYW5kClRlZ3JhMzAgU29Dcy4gVGhlIGludGVyY29ubmVjdCBw cm92aWRlcyBhcmUgcXVpdGUgZ2VuZXJpYyBhbmQgc2hvdWxkIGJlCnN1aXRhYmxlIGZvciBhbGwg VGVncmEgU29DcywgYnV0IGN1cnJlbnRseSBzdXBwb3J0IGlzIGFkZGVkIG9ubHkgZm9yIHRoZXNl CnR3byBnZW5lcmF0aW9ucyBvZiBUZWdyYSBTb0NzLgoKRm9yIHRoZSBzdGFydGVyIG9ubHkgZGlz cGxheSBjb250cm9sbGVycyBhcmUgZ2V0dGluZyBpbnRlcmNvbm5lY3QgQVBJCnN1cHBvcnQsIG90 aGVycyBjb3VsZCBiZSBzdXBwb3J0ZWQgbGF0ZXIgb24uIFRoZSBkaXNwbGF5IGNvbnRyb2xsZXJz CmhhdmUgdGhlIGJpZ2dlc3QgZGVtYW5kIGZvciBpbnRlcmNvbm5lY3QgQVBJIHJpZ2h0IG5vdyBi ZWNhdXNlIGR5bmFtaWMKbWVtb3J5IGZyZXF1ZW5jeSBzY2FsaW5nIGNhbid0IGJlIGRvbmUgc2Fm ZWx5IHdpdGhvdXQgdGFraW5nIGludG8gYWNjb3VudApiYW5kd2lkdGggcmVxdWlyZW1lbnQgZnJv bSB0aGUgZGlzcGxheXMuCgooISkgUGxlYXNlIG5vdGUgdGhhdCB0aGUgRU1DIHBhdGNoZXMgYXJl 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