From: "Milan P. Stanić" <mps-OV3VlZ6014XR7s880joybQ@public.gmane.org>
To: Doug Anderson <dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Cc: Enric Balletbo Serra
<eballetbo-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
"open list:ARM/Rockchip SoC..."
<linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>
Subject: Re: PROBLEM: [drm:analogix_dp_bridge_atomic_enable [analogix_dp]] *ERROR* Failed to disable psr -110
Date: Fri, 10 Apr 2020 21:29:26 +0200 [thread overview]
Message-ID: <20200410192926.GA24668@arya.arvanta.net> (raw)
In-Reply-To: <CAD=FV=WWx2KH+qKvGa5yQW7fZHQ_azd69Eza_Gvs18eQPvfHGg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
Hi,
On Fri, 2020-04-10 at 08:28, Doug Anderson wrote:
> Hi,
>
> On Fri, Apr 10, 2020 at 5:56 AM Enric Balletbo Serra
> <eballetbo-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> >
> > Hi Milan,
> >
> > Right, this is an annoying issue but also known, unfortunately, I
> > personally didn't have time to look at. but it is in my TODO.
>
> Random shot in the dark, but any chance somehow your PHY clock and
> PCLK for the eDP don't match? If they don't then (IIRC) you'll get
> random failures to access eDP registers.
>
> Some history in <https://crrev.com/c/433393>. It looks like the
> changes in that patch are upstream but if something else happened to
> make your PHY and PCLK mismatch it could cause similar symptoms.
>
> ...of course it's always possible (probable) that it's something
> different, but since that was such a weird and hard-to-track-down
> problem I figured I'd at least make sure it wasn't that.
Not sure I understood (I'm not graphic hardware programmer) but I
changed arch/arm64/boot/dts/rockchip/rk3399.dtsi file around line
1367 (current mainline kernel), this:
assigned-clocks =
<&cru PLL_GPLL>, <&cru PLL_CPLL>,
<&cru PLL_NPLL>,
<&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
<&cru PCLK_PERIHP>,
<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
<&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
<&cru ACLK_VIO>, <&cru ACLK_HDCP>,
<&cru ACLK_GIC_PRE>,
<&cru PCLK_DDR>;
assigned-clock-rates =
<594000000>, <800000000>,
<1000000000>,
<150000000>, <75000000>,
<37500000>,
<100000000>, <100000000>,
<50000000>, <600000000>,
<100000000>, <50000000>,
<400000000>, <400000000>,
<200000000>,
<200000000>;
and changed <594000000> to <600000000>
build kernel and it boots but display is blank after boot.
TIA
> -Doug
next prev parent reply other threads:[~2020-04-10 19:29 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-29 20:33 PROBLEM: [drm:analogix_dp_bridge_atomic_enable [analogix_dp]] *ERROR* Failed to disable psr -110 Milan P. Stanić
[not found] ` <20200329203349.GA15121-2zQUq8s2aCOuucbRd6SqTw@public.gmane.org>
2020-04-10 9:57 ` Milan P. Stanić
[not found] ` <20200410095719.GA914-2zQUq8s2aCOuucbRd6SqTw@public.gmane.org>
2020-04-10 12:56 ` Enric Balletbo Serra
[not found] ` <CAFqH_53TsmtSFnUoWixsa4v6GvOi0Korv3p8BJfROhtW0Afw-Q-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2020-04-10 15:28 ` Doug Anderson
[not found] ` <CAD=FV=WWx2KH+qKvGa5yQW7fZHQ_azd69Eza_Gvs18eQPvfHGg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2020-04-10 19:29 ` Milan P. Stanić [this message]
[not found] ` <20200410192926.GA24668-2zQUq8s2aCOuucbRd6SqTw@public.gmane.org>
2020-04-13 15:23 ` Doug Anderson
[not found] ` <CAD=FV=W-5FiZsj-u7V1Kzdo95RaqhE0FQf=nKt7EwyhT5A_RQw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2020-04-14 16:17 ` Enric Balletbo Serra
[not found] ` <CAFqH_50ftrsCZjazu_-DOcC4pqZf2UJ2N7e3HqWitz16jyUUOA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2020-04-14 18:22 ` Milan P. Stanić
[not found] ` <20200414182242.GA1769-2zQUq8s2aCOuucbRd6SqTw@public.gmane.org>
2020-04-17 19:26 ` Milan P. Stanić
[not found] ` <20200417192614.GA8457-2zQUq8s2aCOuucbRd6SqTw@public.gmane.org>
2020-04-25 21:11 ` Milan P. Stanić
[not found] ` <20200425211139.GA18575-2zQUq8s2aCOuucbRd6SqTw@public.gmane.org>
2020-04-28 19:38 ` Milan P. Stanić
-- strict thread matches above, loose matches on Subject: below --
2020-03-19 20:01 Milan P. Stanić
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