From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Subject: [Intel-gfx] [PATCH] drm/i915: Fix indirect context size calculation
Date: Tue, 14 Apr 2020 15:20:00 +0300 [thread overview]
Message-ID: <20200414122000.19353-1-mika.kuoppala@linux.intel.com> (raw)
Hardware needs cacheline count for indirect context size.
Count of zero means that the feature is disabled.
If we only divide size with cacheline bytes, we get
one cacheline short of execution.
Divide by rounding up to a cacheline size so that
hardware executes everything intended.
Bspec: 11739
Fixes: 17ee950df38b ("drm/i915/gen8: Add infrastructure to initialize WA batch buffers")
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 6fbad5e2343f..acbb36ad17ff 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -4739,7 +4739,8 @@ static void init_wa_bb_reg_state(u32 * const regs,
regs[pos_bb_per_ctx + 2] =
(ggtt_offset + wa_ctx->indirect_ctx.offset) |
- (wa_ctx->indirect_ctx.size / CACHELINE_BYTES);
+ DIV_ROUND_UP(wa_ctx->indirect_ctx.size,
+ CACHELINE_BYTES);
regs[pos_bb_per_ctx + 4] =
intel_lr_indirect_ctx_offset(engine) << 6;
--
2.17.1
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next reply other threads:[~2020-04-14 12:20 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-14 12:20 Mika Kuoppala [this message]
2020-04-14 13:51 ` [Intel-gfx] [PATCH] drm/i915: Fix indirect context size calculation Mika Kuoppala
2020-04-14 14:39 ` Chris Wilson
2020-04-14 14:38 ` Chris Wilson
2020-04-14 23:24 ` [Intel-gfx] ✗ Fi.CI.DOCS: warning for " Patchwork
2020-04-14 23:30 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-04-15 14:47 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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