diff for duplicates of <20200414181054.GA6655@bogus> diff --git a/a/1.txt b/N1/1.txt index b5ece6e..bd18d9d 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,11 +1,11 @@ On Fri, 3 Apr 2020 22:22:03 +0200, Thierry Reding wrote: -> From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> +> From: Thierry Reding <treding@nvidia.com> > > The NVIDIA Tegra186 SoC contains an IP block that provides a register > interface for ten timers with a 29-bit counter that can generate one- > shot, periodic or watchdog interrupts. > -> Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> +> Signed-off-by: Thierry Reding <treding@nvidia.com> > --- > Changes in v2: > - add required properties section @@ -17,4 +17,4 @@ On Fri, 3 Apr 2020 22:22:03 +0200, Thierry Reding wrote: > create mode 100644 Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml > -Reviewed-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> +Reviewed-by: Rob Herring <robh@kernel.org> diff --git a/a/content_digest b/N1/content_digest index a79817b..6fb6a7e 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,27 +1,27 @@ "ref\020200403202209.299823-1-thierry.reding@gmail.com\0" "ref\020200403202209.299823-2-thierry.reding@gmail.com\0" - "ref\020200403202209.299823-2-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org\0" - "From\0Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>\0" + "From\0Rob Herring <robh@kernel.org>\0" "Subject\0Re: [PATCH v3 1/7] dt-bindings: timer: Add bindings for NVIDIA Tegra186 timers\0" "Date\0Tue, 14 Apr 2020 13:10:54 -0500\0" - "Cc\0Daniel Lezcano <daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>" - Thomas Gleixner <tglx-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org> - Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> - Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> - Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> - devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - " linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\0" + "To\0Thierry Reding <thierry.reding@gmail.com>\0" + "Cc\0Daniel Lezcano <daniel.lezcano@linaro.org>" + Thomas Gleixner <tglx@linutronix.de> + Thierry Reding <thierry.reding@gmail.com> + Dmitry Osipenko <digetx@gmail.com> + Jon Hunter <jonathanh@nvidia.com> + devicetree@vger.kernel.org + linux-tegra@vger.kernel.org + " linux-kernel@vger.kernel.org\0" "\00:1\0" "b\0" "On Fri, 3 Apr 2020 22:22:03 +0200, Thierry Reding wrote:\n" - "> From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\n" + "> From: Thierry Reding <treding@nvidia.com>\n" "> \n" "> The NVIDIA Tegra186 SoC contains an IP block that provides a register\n" "> interface for ten timers with a 29-bit counter that can generate one-\n" "> shot, periodic or watchdog interrupts.\n" "> \n" - "> Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\n" + "> Signed-off-by: Thierry Reding <treding@nvidia.com>\n" "> ---\n" "> Changes in v2:\n" "> - add required properties section\n" @@ -33,6 +33,6 @@ "> create mode 100644 Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml\n" "> \n" "\n" - Reviewed-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> + Reviewed-by: Rob Herring <robh@kernel.org> -ebe066c0b236bf93107a70dd04d35934c188ebb3533746766f986e006cbd22d2 +ee6a0a57eb6e8748390576e5ec24c41dd528ad22c316f714e4a6e6ba9caf1415
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