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15 Apr 2020 01:08:22 -0700 Date: Wed, 15 Apr 2020 11:04:54 +0300 From: "Lisovskiy, Stanislav" To: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Message-ID: <20200415080454.GA17859@intel.com> References: <20200409154730.18568-1-stanislav.lisovskiy@intel.com> <20200409154730.18568-7-stanislav.lisovskiy@intel.com> <20200414174225.GG6112@intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200414174225.GG6112@intel.com> User-Agent: Mutt/1.9.4 (2018-02-28) Subject: Re: [Intel-gfx] [PATCH v22 06/13] drm/i915: Add pre/post plane updates for SAGV X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com, intel-gfx@lists.freedesktop.org Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Tue, Apr 14, 2020 at 08:42:25PM +0300, Ville Syrj=E4l=E4 wrote: > On Thu, Apr 09, 2020 at 06:47:23PM +0300, Stanislav Lisovskiy wrote: > > Lets have a unified way to handle SAGV changes, > > espoecially considering the upcoming Gen12 changes. > > = > > Current "standard" way of doing this in commit_tail > > is pre/post plane updates, when everything which > > has to be forbidden and not supported in new config > > has to be restricted before update and relaxed after > > plane update. > > = > > Signed-off-by: Stanislav Lisovskiy > > --- > > drivers/gpu/drm/i915/display/intel_display.c | 13 ++++--------- > > drivers/gpu/drm/i915/intel_pm.c | 20 ++++++++++++++++++++ > > drivers/gpu/drm/i915/intel_pm.h | 2 ++ > > 3 files changed, 26 insertions(+), 9 deletions(-) > > = > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu= /drm/i915/display/intel_display.c > > index 70ec301fe6e3..ac7f600c84ca 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > @@ -15349,12 +15349,7 @@ static void intel_atomic_commit_tail(struct in= tel_atomic_state *state) > > = > > intel_set_cdclk_pre_plane_update(state); > > = > > - /* > > - * SKL workaround: bspec recommends we disable the SAGV when we > > - * have more then one pipe enabled > > - */ > > - if (!intel_can_enable_sagv(state)) > > - intel_disable_sagv(dev_priv); > > + intel_sagv_pre_plane_update(state); > > = > > intel_modeset_verify_disabled(dev_priv, state); > > } > > @@ -15451,11 +15446,11 @@ static void intel_atomic_commit_tail(struct i= ntel_atomic_state *state) > > intel_check_cpu_fifo_underruns(dev_priv); > > intel_check_pch_fifo_underruns(dev_priv); > > = > > - if (state->modeset) > > + if (state->modeset) { > > intel_verify_planes(state); > > = > > - if (state->modeset && intel_can_enable_sagv(state)) > > - intel_enable_sagv(dev_priv); > > + intel_sagv_post_plane_update(state); > > + } > > = > > drm_atomic_helper_commit_hw_done(&state->base); > > = > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/int= el_pm.c > > index 41af69ad3edc..d1df288396d8 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -3757,6 +3757,26 @@ intel_disable_sagv(struct drm_i915_private *dev_= priv) > > return 0; > > } > > = > > +void intel_sagv_pre_plane_update(struct intel_atomic_state *state) > > +{ > > + struct drm_i915_private *dev_priv =3D to_i915(state->base.dev); > > + > > + if (!intel_can_enable_sagv(state)) { > > + intel_disable_sagv(dev_priv); > > + return; > > + } > > +} > > + > > +void intel_sagv_post_plane_update(struct intel_atomic_state *state) > > +{ > > + struct drm_i915_private *dev_priv =3D to_i915(state->base.dev); > > + > > + if (intel_can_enable_sagv(state)) { > > + intel_enable_sagv(dev_priv); > > + return; > = > Pointless returns. With those removed Agree, my vision was way to blurry after reshuffling. > = > Reviewed-by: Ville Syrj=E4l=E4 > = > > + } > > +} > > + > > static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *= crtc_state) > > { > > struct drm_i915_private *dev_priv =3D to_i915(crtc_state->uapi.crtc->= dev); > > diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/int= el_pm.h > > index d60a85421c5a..9a6036ab0f90 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.h > > +++ b/drivers/gpu/drm/i915/intel_pm.h > > @@ -44,6 +44,8 @@ void vlv_wm_sanitize(struct drm_i915_private *dev_pri= v); > > bool intel_can_enable_sagv(struct intel_atomic_state *state); > > int intel_enable_sagv(struct drm_i915_private *dev_priv); > > int intel_disable_sagv(struct drm_i915_private *dev_priv); > > +void intel_sagv_pre_plane_update(struct intel_atomic_state *state); > > +void intel_sagv_post_plane_update(struct intel_atomic_state *state); > > bool skl_wm_level_equals(const struct skl_wm_level *l1, > > const struct skl_wm_level *l2); > > bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb, > > -- = > > 2.24.1.485.gad05a3d8e5 > = > -- = > Ville Syrj=E4l=E4 > Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx