All of lore.kernel.org
 help / color / mirror / Atom feed
From: Bjorn Helgaas <helgaas@kernel.org>
To: linux-pci@vger.kernel.org
Cc: linux-kernel@vger.kernel.org,
	"Luís Mendes" <luis.p.mendes@gmail.com>,
	"Todd Poynor" <toddpoynor@google.com>
Subject: Re: [PATCH] PCI: Move Apex Edge TPU class quirk to fix BAR assignment
Date: Wed, 22 Apr 2020 10:58:26 -0500	[thread overview]
Message-ID: <20200422155826.GA222701@google.com> (raw)
In-Reply-To: <20200415001753.145993-1-helgaas@kernel.org>

On Tue, Apr 14, 2020 at 07:17:53PM -0500, Bjorn Helgaas wrote:
> From: Bjorn Helgaas <bhelgaas@google.com>
> 
> Some Google Apex Edge TPU devices have a class code of 0
> (PCI_CLASS_NOT_DEFINED).  This prevents the PCI core from assigning
> resources for the Apex BARs because __dev_sort_resources() ignores
> classless devices, host bridges, and IOAPICs.
> 
> On x86, firmware typically assigns those resources, so this was not a
> problem.  But on some architectures, firmware does *not* assign BARs, and
> since the PCI core didn't do it either, the Apex device didn't work
> correctly:
> 
>   apex 0000:01:00.0: can't enable device: BAR 0 [mem 0x00000000-0x00003fff 64bit pref] not claimed
>   apex 0000:01:00.0: error enabling PCI device
> 
> f390d08d8b87 ("staging: gasket: apex: fixup undefined PCI class") added a
> quirk to fix the class code, but it was in the apex driver, and if the
> driver was built as a module, it was too late to help.
> 
> Move the quirk to the PCI core, where it will always run early enough that
> the PCI core will assign resources if necessary.
> 
> Link: https://lore.kernel.org/r/CAEzXK1r0Er039iERnc2KJ4jn7ySNUOG9H=Ha8TD8XroVqiZjgg@mail.gmail.com
> Fixes: f390d08d8b87 ("staging: gasket: apex: fixup undefined PCI class")
> Reported-by: Luís Mendes <luis.p.mendes@gmail.com>
> Debugged-by: Luís Mendes <luis.p.mendes@gmail.com>
> Tested-by: Luis Mendes <luis.p.mendes@gmail.com>
> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
> Cc: Todd Poynor <toddpoynor@google.com>

Applied to for-linus for v5.7.

> ---
>  drivers/pci/quirks.c                 | 7 +++++++
>  drivers/staging/gasket/apex_driver.c | 7 -------
>  2 files changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> index 28c9a2409c50..ca9ed5774eb1 100644
> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c
> @@ -5567,3 +5567,10 @@ static void pci_fixup_no_d0_pme(struct pci_dev *dev)
>  	dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT);
>  }
>  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x2142, pci_fixup_no_d0_pme);
> +
> +static void apex_pci_fixup_class(struct pci_dev *pdev)
> +{
> +	pdev->class = (PCI_CLASS_SYSTEM_OTHER << 8) | pdev->class;
> +}
> +DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a,
> +			       PCI_CLASS_NOT_DEFINED, 8, apex_pci_fixup_class);
> diff --git a/drivers/staging/gasket/apex_driver.c b/drivers/staging/gasket/apex_driver.c
> index 46199c8ca441..f12f81c8dd2f 100644
> --- a/drivers/staging/gasket/apex_driver.c
> +++ b/drivers/staging/gasket/apex_driver.c
> @@ -570,13 +570,6 @@ static const struct pci_device_id apex_pci_ids[] = {
>  	{ PCI_DEVICE(APEX_PCI_VENDOR_ID, APEX_PCI_DEVICE_ID) }, { 0 }
>  };
>  
> -static void apex_pci_fixup_class(struct pci_dev *pdev)
> -{
> -	pdev->class = (PCI_CLASS_SYSTEM_OTHER << 8) | pdev->class;
> -}
> -DECLARE_PCI_FIXUP_CLASS_HEADER(APEX_PCI_VENDOR_ID, APEX_PCI_DEVICE_ID,
> -			       PCI_CLASS_NOT_DEFINED, 8, apex_pci_fixup_class);
> -
>  static int apex_pci_probe(struct pci_dev *pci_dev,
>  			  const struct pci_device_id *id)
>  {
> -- 
> 2.26.0.110.g2183baf09c-goog
> 

      reply	other threads:[~2020-04-22 15:58 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-15  0:17 [PATCH] PCI: Move Apex Edge TPU class quirk to fix BAR assignment Bjorn Helgaas
2020-04-22 15:58 ` Bjorn Helgaas [this message]

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20200422155826.GA222701@google.com \
    --to=helgaas@kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=luis.p.mendes@gmail.com \
    --cc=toddpoynor@google.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.