From: Andrew Lunn <andrew@lunn.ch>
To: Michael Walle <michael@walle.cc>
Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
Florian Fainelli <f.fainelli@gmail.com>,
Heiner Kallweit <hkallweit1@gmail.com>,
Russell King <linux@armlinux.org.uk>,
"David S . Miller" <davem@davemloft.net>
Subject: Re: [PATCH net-next 3/4] net: phy: bcm54140: apply the workaround on b0 chips
Date: Tue, 28 Apr 2020 23:23:11 +0200 [thread overview]
Message-ID: <20200428212311.GD30459@lunn.ch> (raw)
In-Reply-To: <20200428210854.28088-3-michael@walle.cc>
On Tue, Apr 28, 2020 at 11:08:53PM +0200, Michael Walle wrote:
> The lower three bits of the phy_id specifies the chip stepping. The
> workaround is specifically for the B0 stepping. Apply it only on these
> chips.
>
> Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
next prev parent reply other threads:[~2020-04-28 21:23 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-28 21:08 [PATCH net-next 1/4] net: phy: bcm54140: use genphy_soft_reset() Michael Walle
2020-04-28 21:08 ` [PATCH net-next 2/4] net: phy: bcm54140: fix phy_id_mask Michael Walle
2020-04-28 21:22 ` Andrew Lunn
2020-04-28 22:31 ` Florian Fainelli
2020-04-28 21:08 ` [PATCH net-next 3/4] net: phy: bcm54140: apply the workaround on b0 chips Michael Walle
2020-04-28 21:23 ` Andrew Lunn [this message]
2020-04-28 22:31 ` Florian Fainelli
2020-04-28 21:08 ` [PATCH net-next 4/4] net: phy: bcm54140: add second PHY ID Michael Walle
2020-04-28 21:29 ` Andrew Lunn
2020-04-28 22:08 ` Michael Walle
2020-04-28 22:33 ` Florian Fainelli
2020-04-28 22:28 ` [PATCH net-next 1/4] net: phy: bcm54140: use genphy_soft_reset() Florian Fainelli
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