From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4BF64C83001 for ; Thu, 30 Apr 2020 08:15:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2E9DB2073E for ; Thu, 30 Apr 2020 08:15:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726626AbgD3IPb (ORCPT ); Thu, 30 Apr 2020 04:15:31 -0400 Received: from elvis.franken.de ([193.175.24.41]:33107 "EHLO elvis.franken.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726127AbgD3IPa (ORCPT ); Thu, 30 Apr 2020 04:15:30 -0400 Received: from uucp (helo=alpha) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1jU4Lu-0001S9-00; Thu, 30 Apr 2020 10:15:26 +0200 Received: by alpha.franken.de (Postfix, from userid 1000) id 334B3C0355; Thu, 30 Apr 2020 10:13:57 +0200 (CEST) Date: Thu, 30 Apr 2020 10:13:57 +0200 From: Thomas Bogendoerfer To: Huacai Chen Cc: "open list:MIPS" , Fuxin Zhang , Zhangjin Wu , Jiaxun Yang Subject: Re: [PATCH V2] MIPS: perf: Add hardware perf events support for new Loongson-3 Message-ID: <20200430081357.GA7626@alpha.franken.de> References: <1588145170-9451-1-git-send-email-chenhc@lemote.com> <20200429182231.GA21158@alpha.franken.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org On Thu, Apr 30, 2020 at 03:30:55PM +0800, Huacai Chen wrote: > Hi, Thomas, > > On Thu, Apr 30, 2020 at 2:33 AM Thomas Bogendoerfer > wrote: > > > > On Wed, Apr 29, 2020 at 03:26:10PM +0800, Huacai Chen wrote: > > > New Loongson-3 means Loongson-3A R2 (Loongson-3A2000) and newer CPUs. > > > Loongson-3 processors have three types of PMU types (so there are three > > > event maps): Loongson-3A1000/Loonngson-3B1000/Loongson-3B1500 is Type-1, > > > Loongson-3A2000/Loongson-3A3000 is Type-2, Loongson-3A4000+ is Type-3. > > > > > > Signed-off-by: Huacai Chen > > > --- > > > .../asm/mach-loongson64/cpu-feature-overrides.h | 1 + > > > arch/mips/kernel/perf_event_mipsxx.c | 358 +++++++++++++++++++-- > > > > checkpatch warns about missing break/fallthrough statement and indention > > problems, could please look at this ? And as all the new code is only > > usefull for loongsoon CPUs could you try to only compile it in, if it's > > enabled for the image ? > OK, I will solve the "fallthrough" warnings and indention warnings. > But the other problem is I should use #ifdef CONFIG_CPU_LOONGSON64 to > guard all new code in this file? I remember that Paul Burton suggest > us to avoid use #ifdef and use runtime detection instead. if you do the cpu checks for current_cpu_type() == CPU_LOONGSON64 the compiler will eliminate not needed cpu code. Looks like most of the new code is done inside case CPU_LOONGSON64 blocks, so that is fine. Could you check how much size increase you get for a non loongson64 target with your patch ? Thomas. -- Crap can work. Given enough thrust pigs will fly, but it's not necessarily a good idea. [ RFC1925, 2.3 ]