From: Max Filippov <jcmvbkbc@gmail.com>
To: qemu-devel@nongnu.org
Cc: Max Filippov <jcmvbkbc@gmail.com>, qemu-stable@nongnu.org
Subject: [PATCH] target/xtensa: work around missing SR definitions
Date: Thu, 30 Apr 2020 04:39:15 -0700 [thread overview]
Message-ID: <20200430113915.19550-1-jcmvbkbc@gmail.com> (raw)
Xtensa configuration overlays for recent releases may have special
registers for which [rwx]sr opcodes are defined, but they are not listed
as SR in xtensa_sysreg_name and associated functions. As a result
generic translate_[rwx]sr* functions generate access to uninitialized
cpu_SR causing segfault at runtime.
Don't try to access cpu_SR for such registers, ignore writes and return
0 for reads.
Cc: qemu-stable@nongnu.org
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
target/xtensa/translate.c | 48 +++++++++++++++++++++++++++------------
1 file changed, 34 insertions(+), 14 deletions(-)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index e0beaf7abbbd..546d2fa2facf 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -2191,7 +2191,11 @@ static void translate_rsil(DisasContext *dc, const OpcodeArg arg[],
static void translate_rsr(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]);
+ if (sr_name[par[0]]) {
+ tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]);
+ } else {
+ tcg_gen_movi_i32(arg[0].out, 0);
+ }
}
static void translate_rsr_ccount(DisasContext *dc, const OpcodeArg arg[],
@@ -2563,13 +2567,17 @@ static void translate_wrmsk_expstate(DisasContext *dc, const OpcodeArg arg[],
static void translate_wsr(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- tcg_gen_mov_i32(cpu_SR[par[0]], arg[0].in);
+ if (sr_name[par[0]]) {
+ tcg_gen_mov_i32(cpu_SR[par[0]], arg[0].in);
+ }
}
static void translate_wsr_mask(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- tcg_gen_andi_i32(cpu_SR[par[0]], arg[0].in, par[2]);
+ if (sr_name[par[0]]) {
+ tcg_gen_andi_i32(cpu_SR[par[0]], arg[0].in, par[2]);
+ }
}
static void translate_wsr_acchi(DisasContext *dc, const OpcodeArg arg[],
@@ -2775,23 +2783,31 @@ static void translate_xor(DisasContext *dc, const OpcodeArg arg[],
static void translate_xsr(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- TCGv_i32 tmp = tcg_temp_new_i32();
+ if (sr_name[par[0]]) {
+ TCGv_i32 tmp = tcg_temp_new_i32();
- tcg_gen_mov_i32(tmp, arg[0].in);
- tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]);
- tcg_gen_mov_i32(cpu_SR[par[0]], tmp);
- tcg_temp_free(tmp);
+ tcg_gen_mov_i32(tmp, arg[0].in);
+ tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]);
+ tcg_gen_mov_i32(cpu_SR[par[0]], tmp);
+ tcg_temp_free(tmp);
+ } else {
+ tcg_gen_movi_i32(arg[0].out, 0);
+ }
}
static void translate_xsr_mask(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- TCGv_i32 tmp = tcg_temp_new_i32();
+ if (sr_name[par[0]]) {
+ TCGv_i32 tmp = tcg_temp_new_i32();
- tcg_gen_mov_i32(tmp, arg[0].in);
- tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]);
- tcg_gen_andi_i32(cpu_SR[par[0]], tmp, par[2]);
- tcg_temp_free(tmp);
+ tcg_gen_mov_i32(tmp, arg[0].in);
+ tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]);
+ tcg_gen_andi_i32(cpu_SR[par[0]], tmp, par[2]);
+ tcg_temp_free(tmp);
+ } else {
+ tcg_gen_movi_i32(arg[0].out, 0);
+ }
}
static void translate_xsr_ccount(DisasContext *dc, const OpcodeArg arg[],
@@ -2819,7 +2835,11 @@ static void translate_xsr_ccount(DisasContext *dc, const OpcodeArg arg[],
{ \
TCGv_i32 tmp = tcg_temp_new_i32(); \
\
- tcg_gen_mov_i32(tmp, cpu_SR[par[0]]); \
+ if (sr_name[par[0]]) { \
+ tcg_gen_mov_i32(tmp, cpu_SR[par[0]]); \
+ } else { \
+ tcg_gen_movi_i32(tmp, 0); \
+ } \
translate_wsr_##name(dc, arg, par); \
tcg_gen_mov_i32(arg[0].out, tmp); \
tcg_temp_free(tmp); \
--
2.20.1
next reply other threads:[~2020-04-30 11:41 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-30 11:39 Max Filippov [this message]
2020-04-30 22:07 ` [PATCH] target/xtensa: work around missing SR definitions no-reply
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