From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 5/9] drm/i915/gen12: Flush AMFS
Date: Thu, 30 Apr 2020 18:47:31 +0300 [thread overview]
Message-ID: <20200430154735.22434-5-mika.kuoppala@linux.intel.com> (raw)
In-Reply-To: <20200430154735.22434-1-mika.kuoppala@linux.intel.com>
To ensure that we have global observation point wrt to
all data, flush amfs.
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
drivers/gpu/drm/i915/gt/intel_lrc.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index 98b39e65aed9..69979cc86caa 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -223,6 +223,7 @@
#define PIPE_CONTROL_COMMAND_CACHE_INVALIDATE (1<<29) /* gen11+ */
#define PIPE_CONTROL_TILE_CACHE_FLUSH (1<<28) /* gen11+ */
#define PIPE_CONTROL_FLUSH_L3 (1<<27)
+#define PIPE_CONTROL_FLUSH_AMFS (1<<25) /* gen12+ */
#define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */
#define PIPE_CONTROL_MMIO_WRITE (1<<23)
#define PIPE_CONTROL_STORE_DATA_INDEX (1<<21)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 0bbce218157f..b47230583494 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -4555,6 +4555,7 @@ static int gen12_emit_flush_render(struct i915_request *request,
flags |= PIPE_CONTROL_L3_FABRIC_FLUSH;
flags |= PIPE_CONTROL_TILE_CACHE_FLUSH;
flags |= PIPE_CONTROL_FLUSH_L3;
+ flags |= PIPE_CONTROL_FLUSH_AMFS;
flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
/* Wa_1409600907:tgl */
@@ -4771,6 +4772,7 @@ gen12_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs)
PIPE_CONTROL_L3_FABRIC_FLUSH |
PIPE_CONTROL_TILE_CACHE_FLUSH |
PIPE_CONTROL_FLUSH_L3 |
+ PIPE_CONTROL_FLUSH_AMFS |
PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
PIPE_CONTROL_DEPTH_CACHE_FLUSH |
/* Wa_1409600907:tgl */
--
2.17.1
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next prev parent reply other threads:[~2020-04-30 15:48 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-30 15:47 [Intel-gfx] [PATCH 1/9] Revert "drm/i915/tgl: Include ro parts of l3 to invalidate" Mika Kuoppala
2020-04-30 15:47 ` [Intel-gfx] [PATCH 2/9] drm/i915/gen12: Fix HDC pipeline flush Mika Kuoppala
2020-05-03 18:24 ` Chris Wilson
2020-05-03 21:20 ` Chris Wilson
2020-05-05 21:02 ` D Scott Phillips
2020-04-30 15:47 ` [Intel-gfx] [PATCH 3/9] drm/i915/gen12: Add L3 fabric flush Mika Kuoppala
2020-05-03 21:22 ` Chris Wilson
2020-04-30 15:47 ` [Intel-gfx] [PATCH 4/9] drm/i915/gen12: Flush L3 Mika Kuoppala
2020-05-03 21:25 ` Chris Wilson
2020-05-05 8:45 ` Mika Kuoppala
2020-04-30 15:47 ` Mika Kuoppala [this message]
2020-05-03 21:26 ` [Intel-gfx] [PATCH 5/9] drm/i915/gen12: Flush AMFS Chris Wilson
2020-04-30 15:47 ` [Intel-gfx] [PATCH 6/9] drm/i915/gen12: Invalidate indirect state pointers Mika Kuoppala
2020-05-03 21:29 ` Chris Wilson
2020-05-05 20:53 ` D Scott Phillips
2020-04-30 15:47 ` [Intel-gfx] [PATCH 7/9] drm/i915/gen12: Wait on previous flush on invalidate Mika Kuoppala
2020-05-03 21:31 ` Chris Wilson
2020-04-30 15:47 ` [Intel-gfx] [PATCH 8/9] drm/i915/gen12: Invalidate media state Mika Kuoppala
2020-05-03 21:32 ` Chris Wilson
2020-04-30 15:47 ` [Intel-gfx] [PATCH 9/9] drm/i915/gen12: Flush LLC Mika Kuoppala
2020-05-03 21:36 ` Chris Wilson
2020-04-30 16:01 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/9] Revert "drm/i915/tgl: Include ro parts of l3 to invalidate" Patchwork
2020-04-30 16:25 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-04-30 16:30 ` Chris Wilson
2020-04-30 23:40 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-05-03 21:18 ` [Intel-gfx] [PATCH 1/9] " Chris Wilson
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