From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
"Jason Wang" <jasowang@redhat.com>,
"Markus Armbruster" <armbru@redhat.com>,
qemu-devel@nongnu.org, qemu-arm@nongnu.org,
"Tong Ho" <tong.ho@xilinx.com>,
"Alistair Francis" <Alistair.Francis@wdc.com>,
"Philippe Mathieu-Daudé" <philmd@redhat.com>,
"Ramon Fried" <rfried.dev@gmail.com>
Subject: Re: [PATCH v2 08/10] net: cadence_gem: Update the reset value for interrupt mask register
Date: Mon, 4 May 2020 17:27:46 +0200 [thread overview]
Message-ID: <20200504152746.GH5519@toto> (raw)
In-Reply-To: <1588601168-27576-9-git-send-email-sai.pavan.boddu@xilinx.com>
On Mon, May 04, 2020 at 07:36:06PM +0530, Sai Pavan Boddu wrote:
> Mask all interrupt on reset.
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
>
> Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
> ---
> hw/net/cadence_gem.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
> index 9eb72a2..ac3a553 100644
> --- a/hw/net/cadence_gem.c
> +++ b/hw/net/cadence_gem.c
> @@ -1348,6 +1348,7 @@ static void gem_reset(DeviceState *d)
> s->regs[GEM_DESCONF2] = 0x2ab12800;
> s->regs[GEM_DESCONF5] = 0x002f2045;
> s->regs[GEM_DESCONF6] = GEM_DESCONF6_64B_MASK;
> + s->regs[GEM_INT_Q1_MASK] = 0x00000CE6;
>
> if (s->num_priority_queues > 1) {
> queues_mask = MAKE_64BIT_MASK(1, s->num_priority_queues - 1);
> --
> 2.7.4
>
next prev parent reply other threads:[~2020-05-04 15:28 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-04 14:05 [PATCH v2 00/10] Cadence GEM Fixes Sai Pavan Boddu
2020-05-04 14:05 ` [PATCH v2 01/10] net: cadence_gem: Fix debug statements Sai Pavan Boddu
2020-05-04 14:39 ` Edgar E. Iglesias
2020-05-06 9:55 ` Sai Pavan Boddu
2020-05-04 14:06 ` [PATCH v2 02/10] net: cadence_gem: Fix the queue address update during wrap around Sai Pavan Boddu
2020-05-04 14:43 ` Edgar E. Iglesias
2020-05-04 14:06 ` [PATCH v2 03/10] net: cadence_gem: Fix irq update w.r.t queue Sai Pavan Boddu
2020-05-04 14:32 ` Edgar E. Iglesias
2020-05-04 14:06 ` [PATCH v2 04/10] net: cadence_gem: Define access permission for interrupt registers Sai Pavan Boddu
2020-05-04 14:57 ` Edgar E. Iglesias
2020-05-06 10:40 ` Sai Pavan Boddu
2020-05-04 14:06 ` [PATCH v2 05/10] net: cadence_gem: Set ISR according to queue in use Sai Pavan Boddu
2020-05-04 15:02 ` Edgar E. Iglesias
2020-05-06 11:11 ` Sai Pavan Boddu
2020-05-04 14:06 ` [PATCH v2 06/10] net: cadence_gem: Add support for jumbo frames Sai Pavan Boddu
2020-05-04 15:23 ` Edgar E. Iglesias
2020-05-04 14:06 ` [PATCH v2 07/10] net: cadnece_gem: Update irq_read_clear field of designcfg_debug1 reg Sai Pavan Boddu
2020-05-04 15:26 ` Edgar E. Iglesias
2020-05-04 14:06 ` [PATCH v2 08/10] net: cadence_gem: Update the reset value for interrupt mask register Sai Pavan Boddu
2020-05-04 15:27 ` Edgar E. Iglesias [this message]
2020-05-04 14:06 ` [PATCH v2 09/10] net: cadence_gem: TX_LAST bit should be set by guest Sai Pavan Boddu
2020-05-04 15:31 ` Edgar E. Iglesias
2020-05-04 14:06 ` [PATCH v2 10/10] net: cadence_gem: Fix RX address filtering Sai Pavan Boddu
2020-05-04 15:33 ` Edgar E. Iglesias
2020-05-04 15:50 ` [PATCH v2 00/10] Cadence GEM Fixes Ramon Fried
2020-05-04 15:50 ` Ramon Fried
2020-05-04 17:15 ` Sai Pavan Boddu
2020-05-04 17:15 ` Sai Pavan Boddu
2020-05-05 8:31 ` no-reply
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