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From: Alexey Dobriyan <adobriyan@gmail.com>
To: Keith Busch <kbusch@kernel.org>
Cc: axboe@fb.com, John Garry <john.garry@huawei.com>,
	hch@lst.de, linux-nvme@lists.infradead.org, sagi@grimberg.me
Subject: Re: [PATCH] nvme-pci: slimmer CQ head update
Date: Wed, 6 May 2020 16:24:29 +0300	[thread overview]
Message-ID: <20200506132429.GA21451@avx2> (raw)
In-Reply-To: <20200506124701.GA54933@C02WT3WMHTD6>

On Wed, May 06, 2020 at 06:47:01AM -0600, Keith Busch wrote:
> On Wed, May 06, 2020 at 12:03:35PM +0100, John Garry wrote:
> > On 29/02/2020 05:53, Keith Busch wrote:
> > > On Fri, Feb 28, 2020 at 09:45:19PM +0300, Alexey Dobriyan wrote:
> > > >   static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
> > > >   {
> > > > -	if (nvmeq->cq_head == nvmeq->q_depth - 1) {
> > > > +	if (++nvmeq->cq_head == nvmeq->q_depth) {
> > 
> > I figure momentarily nvmeq->cq_head may transition to equal nvmeq->q_depth
> > and then to 0, which causes an out-of-bounds access here:
> > 
> > static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
> > {
> > 	return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
> > 			nvmeq->cq_phase;
> > }
> 
> Thanks for the notice, your analysis sounds correct to me.
> 
> Ideally we wouldn't let the irq check happen while the threaded
> handler is running, but that is a bit risky to introduce at this
> point. I'm okay with reverting to fix this issue.

Pre-increment is still beneficial, should be done in register.
Please, test.


Signed-off-by: Alexey Dobriyan <adobriyan@gmail.com>
---

 drivers/nvme/host/pci.c |    9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

--- a/drivers/nvme/host/pci.c
+++ b/drivers/nvme/host/pci.c
@@ -973,9 +973,16 @@ static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
 
 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
 {
-	if (++nvmeq->cq_head == nvmeq->q_depth) {
+	/*
+	 * Can't pre-increment ->cq_head directly.
+	 * It must be in [0, ->q_depth) range at all times.
+	 */
+	u16 tmp = READ_ONCE(nvmeq->cq_head);
+	if (++tmp == nvmeq->q_depth) {
 		nvmeq->cq_head = 0;
 		nvmeq->cq_phase ^= 1;
+	} else {
+		nvmeq->cq_head = tmp;
 	}
 }
 

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  reply	other threads:[~2020-05-06 13:24 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-28 18:45 [PATCH] nvme-pci: slimmer CQ head update Alexey Dobriyan
2020-02-29  5:53 ` Keith Busch
2020-05-06 11:03   ` John Garry
2020-05-06 12:47     ` Keith Busch
2020-05-06 13:24       ` Alexey Dobriyan [this message]
2020-05-06 13:44         ` John Garry
2020-05-06 14:01           ` Alexey Dobriyan
2020-05-06 14:35           ` Christoph Hellwig
2020-05-06 16:26             ` John Garry
2020-05-06 16:31               ` Will Deacon
2020-05-06 16:52                 ` Robin Murphy
2020-05-06 17:02                   ` John Garry
2020-05-07  8:18                     ` John Garry
2020-05-07 11:04                       ` Robin Murphy
2020-05-07 13:55                         ` John Garry
2020-05-07 14:23                           ` Keith Busch
2020-05-07 15:11                             ` John Garry
2020-05-07 15:35                               ` Keith Busch
2020-05-07 15:41                                 ` John Garry
2020-05-08 16:16                                   ` Keith Busch
2020-05-08 17:04                                     ` John Garry
2020-05-07 16:26                                 ` Robin Murphy
2020-05-07 17:35                                   ` Keith Busch
2020-05-07 17:44                                     ` Will Deacon
2020-05-07 18:06                                       ` Keith Busch
2020-05-08 11:40                                         ` Will Deacon
2020-05-08 14:07                                           ` Keith Busch
2020-05-08 15:34                                             ` Keith Busch
2020-05-06 14:44         ` Keith Busch
2020-05-07 15:58           ` Keith Busch
2020-05-07 20:07             ` [PATCH] nvme-pci: fix "slimmer CQ head update" Alexey Dobriyan

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