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07 May 2020 04:59:35 -0700 Received: by stinkbox (sSMTP sendmail emulation); Thu, 07 May 2020 14:59:34 +0300 Date: Thu, 7 May 2020 14:59:34 +0300 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Matt Roper Message-ID: <20200507115934.GC6112@intel.com> References: <20200504225227.464666-1-matthew.d.roper@intel.com> <20200504225227.464666-13-matthew.d.roper@intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200504225227.464666-13-matthew.d.roper@intel.com> X-Patchwork-Hint: comment User-Agent: Mutt/1.10.1 (2018-07-13) Subject: Re: [Intel-gfx] [PATCH v2 12/22] drm/i915/rkl: Check proper SDEISR bits for TC1 and TC2 outputs X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org, Lucas De Marchi Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Mon, May 04, 2020 at 03:52:17PM -0700, Matt Roper wrote: > When Rocket Lake is paired with a TGP PCH, the last two outputs utilize > the TC1 and TC2 hpd pins, even though these are combo outputs. > = > Bspec: 49181 > Cc: Lucas De Marchi > Signed-off-by: Matt Roper > --- > drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i9= 15/display/intel_dp.c > index 6952b0295096..d32bbcd99b8a 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -6172,8 +6172,12 @@ static bool bxt_digital_port_connected(struct inte= l_encoder *encoder) > static bool intel_combo_phy_connected(struct drm_i915_private *dev_priv, > enum phy phy) > { > - if (HAS_PCH_MCC(dev_priv) && phy =3D=3D PHY_C) > - return intel_de_read(dev_priv, SDEISR) & SDE_TC_HOTPLUG_ICP(PORT_TC1); > + if (IS_ROCKETLAKE(dev_priv) && phy >=3D PHY_C) > + return intel_de_read(dev_priv, SDEISR) & > + SDE_TC_HOTPLUG_ICP(phy - PHY_C); > + else if (HAS_PCH_MCC(dev_priv) && phy =3D=3D PHY_C) > + return intel_de_read(dev_priv, SDEISR) & > + SDE_TC_HOTPLUG_ICP(PORT_TC1); Most of this mess is going to disappear as soon as I can land https://patchwork.freedesktop.org/series/72348/ So assuming the hpd[] thing gets correctly populated we no longer need any hack like these. > = > return intel_de_read(dev_priv, SDEISR) & SDE_DDI_HOTPLUG_ICP(phy); > } > -- = > 2.24.1 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx