From: Jon Derrick <jonathan.derrick@intel.com>
To: <linux-pci@vger.kernel.org>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
Russell King <rmk+kernel@armlinux.org.uk>,
Bjorn Helgaas <helgaas@kernel.org>,
Christoph Hellwig <hch@lst.de>, Rob Herring <robh@kernel.org>,
Jon Derrick <jonathan.derrick@intel.com>
Subject: [PATCH v2 1/4] PCI: pci-bridge-emul: Fix PCIe bit conflicts
Date: Mon, 11 May 2020 12:21:14 -0400 [thread overview]
Message-ID: <20200511162117.6674-2-jonathan.derrick@intel.com> (raw)
In-Reply-To: <20200511162117.6674-1-jonathan.derrick@intel.com>
This patch fixes two bit conflicts in the pci-bridge-emul driver:
1. Bit 3 of Device Status (19 of Device Control) is marked as both
Write-1-to-Clear and Read-Only. It should be Write-1-to-Clear.
The Read-Only and Reserved bitmasks are shifted by 1 bit due to this
error.
2. Bit 12 of Slot Control is marked as both Read-Write and Reserved.
It should be Read-Write.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Jon Derrick <jonathan.derrick@intel.com>
---
drivers/pci/pci-bridge-emul.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/pci-bridge-emul.c b/drivers/pci/pci-bridge-emul.c
index 4f4f54bc732e..faa414655f33 100644
--- a/drivers/pci/pci-bridge-emul.c
+++ b/drivers/pci/pci-bridge-emul.c
@@ -185,8 +185,8 @@ static const struct pci_bridge_reg_behavior pcie_cap_regs_behavior[] = {
* RO, the rest is reserved
*/
.w1c = GENMASK(19, 16),
- .ro = GENMASK(20, 19),
- .rsvd = GENMASK(31, 21),
+ .ro = GENMASK(21, 20),
+ .rsvd = GENMASK(31, 22),
},
[PCI_EXP_LNKCAP / 4] = {
@@ -226,7 +226,7 @@ static const struct pci_bridge_reg_behavior pcie_cap_regs_behavior[] = {
PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC) << 16,
.ro = (PCI_EXP_SLTSTA_MRLSS | PCI_EXP_SLTSTA_PDS |
PCI_EXP_SLTSTA_EIS) << 16,
- .rsvd = GENMASK(15, 12) | (GENMASK(15, 9) << 16),
+ .rsvd = GENMASK(15, 13) | (GENMASK(15, 9) << 16),
},
[PCI_EXP_RTCTL / 4] = {
--
2.18.1
next prev parent reply other threads:[~2020-05-11 16:37 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-11 16:21 [PATCH v2 0/4] Align PCI Emul Bridge to PCIe 5.0 Jon Derrick
2020-05-11 16:21 ` Jon Derrick [this message]
2020-05-11 16:21 ` [PATCH v2 2/4] PCI: pci-bridge-emul: Fix Root Cap/Status comment Jon Derrick
2020-05-11 16:21 ` [PATCH v2 3/4] PCI: pci-bridge-emul: Update for PCIe 5.0 r1.0 Jon Derrick
2020-05-20 22:39 ` Rob Herring
2020-05-11 16:21 ` [PATCH v2 4/4] PCI: pci-bridge-emul: Eliminate the 'reserved' member Jon Derrick
2020-05-20 22:41 ` Rob Herring
2020-05-22 11:42 ` [PATCH v2 0/4] Align PCI Emul Bridge to PCIe 5.0 Lorenzo Pieralisi
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200511162117.6674-2-jonathan.derrick@intel.com \
--to=jonathan.derrick@intel.com \
--cc=hch@lst.de \
--cc=helgaas@kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=lorenzo.pieralisi@arm.com \
--cc=rmk+kernel@armlinux.org.uk \
--cc=robh@kernel.org \
--cc=thomas.petazzoni@bootlin.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.