Re: [PATCH 1/2] dt-bindings: pinctrl: qcom: Add sm8250 pinctrl bindings

[Bjorn Andersson <bjorn.andersson@linaro.org>]

On Wed 29 Apr 14:34 PDT 2020, Rob Herring wrote:
> On Thu, Apr 16, 2020 at 11:19:06PM -0700, Bjorn Andersson wrote:
> > diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml
[..]
> > +#PIN CONFIGURATION NODES
> > +patternProperties:
> > +  '^.*$':
> > +    if:
> > +      type: object
> > +    then:
> 
> Needs a $ref to the standard properties.
> 
> Would be good to show a child node in the example too. (And try having 
> an error in a standard property type to verify you get an error).
> 

Finally looked into this. By $ref'ing pinmux-node.yaml I can drop pins
and function from below properties, and by $ref'ing pincfg-node.yaml I
can drop the pinconf entries listed.

But how do I $ref both?

What's the appropriate method for amending pins, function and
drive-strength with the more specific value set? Should I both $ref them
and list them here?

How do I limit which standard properties are actually supported in this
binding?

Thanks,
Bjorn

> > +      properties:
> > +        pins:
> > +          description:
> > +            List of gpio pins affected by the properties specified in this
> > +            subnode.
> > +          items:
> > +            oneOf:
> > +              - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$"
> > +              - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
> > +          minItems: 1
> > +          maxItems: 36
> > +
> > +        function:
> > +          description:
> > +            Specify the alternative function to be configured for the specified
> > +            pins.
> > +
> > +          enum: [ aoss_cti, atest, audio_ref, cam_mclk, cci_async, cci_i2c,
> > +            cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, cri_trng,
> > +            cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
> > +            ddr_pxi2, ddr_pxi3, dp_hot, dp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, gpio,
> > +            ibi_i3c, jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsync0,
> > +            mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_data1,
> > +            mi2s0_sck, mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws,
> > +            mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, pci_e0, pci_e1,
> > +            pci_e2, phase_flag, pll_bist, pll_bypassnl, pll_clk, pll_reset,
> > +            pri_mi2s, prng_rosc, qdss_cti, qdss_gpio, qspi0, qspi1, qspi2, qspi3,
> > +            qspi_clk, qspi_cs, qup0, qup1, qup10, qup11, qup12, qup13, qup14,
> > +            qup15, qup16, qup17, qup18, qup19, qup2, qup3, qup4, qup5, qup6,
> > +            qup7, qup8, qup9, qup_l4, qup_l5, qup_l6, sd_write, sdc40, sdc41,
> > +            sdc42, sdc43, sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu, tgu_ch0, tgu_ch1,
> > +            tgu_ch2, tgu_ch3, tsense_pwm1, tsense_pwm2, tsif0_clk, tsif0_data,
> > +            tsif0_en, tsif0_error, tsif0_sync, tsif1_clk, tsif1_data, tsif1_en,
> > +            tsif1_error, tsif1_sync, usb2phy_ac, usb_phy, vsense_trigger ]
> > +
> > +        drive-strength:
> > +          enum: [2, 4, 6, 8, 10, 12, 14, 16]
> > +          default: 2
> > +          description:
> > +            Selects the drive strength for the specified pins, in mA.
> > +
> > +        bias-pull-down: true
> > +
> > +        bias-pull-up: true
> > +
> > +        bias-disable: true
> > +
> > +        output-high: true
> > +
> > +        output-low: true
> > +
> > +      required:
> > +        - pins
> > +        - function
> > +
> > +      additionalProperties: false
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - reg-names
> > +  - interrupts
> > +  - interrupt-controller
> > +  - '#interrupt-cells'
> > +  - gpio-controller
> > +  - '#gpio-cells'
> > +  - gpio-ranges
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +        #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +        pinctrl@1f00000 {
> > +                compatible = "qcom,sm8250-pinctrl";
> > +                reg = <0x0f100000 0x300000>,
> > +                      <0x0f500000 0x300000>,
> > +                      <0x0f900000 0x300000>;
> > +                reg-names = "west", "south", "north";
> > +                interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> > +                gpio-controller;
> > +                #gpio-cells = <2>;
> > +                interrupt-controller;
> > +                #interrupt-cells = <2>;
> > +                gpio-ranges = <&tlmm 0 0 180>;
> > +                wakeup-parent = <&pdc>;
> > +        };
> > -- 
> > 2.24.0
> >