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Received: from shell.armlinux.org.uk ([fd8f:7570:feb6:1:5054:ff:fe00:4ec]:60542) by pandora.armlinux.org.uk with esmtpsa (TLSv1.2:ECDHE-RSA-AES256-GCM-SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jZNSZ-00026B-TD; Fri, 15 May 2020 00:40:16 +0100 Received: from linux by shell.armlinux.org.uk with local (Exim 4.92) (envelope-from ) id 1jZNSY-0000z1-21; Fri, 15 May 2020 00:40:14 +0100 Date: Fri, 15 May 2020 00:40:14 +0100 From: Russell King - ARM Linux admin To: Arnd Bergmann Subject: Re: ARM: static kernel in vmalloc space Message-ID: <20200514234013.GQ1551@shell.armlinux.org.uk> References: <20200504091018.GA24897@afzalpc> <20200511142113.GA31707@afzalpc> <20200512104758.GA12980@afzalpc> <20200514111755.GA4997@afzalpc> <20200514162535.GP1551@shell.armlinux.org.uk> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200514_164021_934946_5AED799C X-CRM114-Status: GOOD ( 14.50 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: afzal mohammed , "linux-kernel@vger.kernel.org" , Linux ARM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, May 14, 2020 at 11:12:01PM +0200, Arnd Bergmann wrote: > On Thu, May 14, 2020 at 6:25 PM Russell King - ARM Linux admin > wrote: > > On Thu, May 14, 2020 at 02:41:11PM +0200, Arnd Bergmann wrote: > > > On Thu, May 14, 2020 at 1:18 PM afzal mohammed wrote: > > > > It's clearly possible to do something very similar for older chips > > > (v6 or v7 without LPAE, possibly even v5), it just gets harder > > > while providing less benefit. > > > > Forget about doing this for anything without a PIPT cache - or you're > > going to end up having to flush the data cache each time you enter or > > exit the kernel. > > Right, let's forget I said anything about v5 or earlier ;-) > > I expected the non-aliasing VIPT caches to work the same as PIPT, can > you clarify if there is something to be aware of for those? I see that some > ARMv8 chips and most ARMv6 chips (not OMAP2 and Realview) are > of that kind, and at we clearly don't want to break running on ARMv8 at > least. There are some aliasing VIPT implementations on ARMv6, but I don't remember how common. > Anyway my point was that it's best to only do it for LPAE anyway, everything > else being a distraction, as the only non-LPAE SoCs I could find with > support for over 2GB are some of the higher-end i.MX6 versions and the > original highbank. Yep. -- RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTC broadband for 0.8mile line in suburbia: sync at 10.2Mbps down 587kbps up _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.0 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92E57C433DF for ; Thu, 14 May 2020 23:40:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 67C452065C for ; Thu, 14 May 2020 23:40:24 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=armlinux.org.uk header.i=@armlinux.org.uk header.b="NB7CejOb" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728409AbgENXkX (ORCPT ); Thu, 14 May 2020 19:40:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36922 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726163AbgENXkX (ORCPT ); Thu, 14 May 2020 19:40:23 -0400 Received: from pandora.armlinux.org.uk (pandora.armlinux.org.uk [IPv6:2001:4d48:ad52:3201:214:fdff:fe10:1be6]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D8460C061A0C for ; Thu, 14 May 2020 16:40:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=armlinux.org.uk; s=pandora-2019; h=Sender:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=w6BkmSCK+9PvyslXlTzZk3UIk7P2/MFM4deljPFam9A=; b=NB7CejObDlLA77BJZUE81lycY MeDeTt5CYKPIKdhx9O50BLP04pUP9vAZJFhY/TWIj9EWXUt1odSpUbJPGCye+BD/5Ps/yfCG+LR6W 7sU725RS2Rw5rnS9SCCeA6LPtl6bJ0hl2FM9oxM+9ZB9GHrpNYtUFgvZax6TEVCZoRkEbJtW+BKhI mOKX7L8AqEQp3ULi3r3Japa6hJYqtoCsNaPCe5eew+wkv5h1eF1SL1TvHCP03k3CF7U5559kiHGjQ 1O1O7A/oUW98eQkLHRFGYZUUxyfoIDIehKaJDQthWBXknuJEgaEzj0W8MzD19UWwr1GpBhet4es3k wtnkXT9mA==; Received: from shell.armlinux.org.uk ([fd8f:7570:feb6:1:5054:ff:fe00:4ec]:60542) by pandora.armlinux.org.uk with esmtpsa (TLSv1.2:ECDHE-RSA-AES256-GCM-SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jZNSZ-00026B-TD; Fri, 15 May 2020 00:40:16 +0100 Received: from linux by shell.armlinux.org.uk with local (Exim 4.92) (envelope-from ) id 1jZNSY-0000z1-21; Fri, 15 May 2020 00:40:14 +0100 Date: Fri, 15 May 2020 00:40:14 +0100 From: Russell King - ARM Linux admin To: Arnd Bergmann Cc: afzal mohammed , Linux ARM , "linux-kernel@vger.kernel.org" Subject: Re: ARM: static kernel in vmalloc space Message-ID: <20200514234013.GQ1551@shell.armlinux.org.uk> References: <20200504091018.GA24897@afzalpc> <20200511142113.GA31707@afzalpc> <20200512104758.GA12980@afzalpc> <20200514111755.GA4997@afzalpc> <20200514162535.GP1551@shell.armlinux.org.uk> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, May 14, 2020 at 11:12:01PM +0200, Arnd Bergmann wrote: > On Thu, May 14, 2020 at 6:25 PM Russell King - ARM Linux admin > wrote: > > On Thu, May 14, 2020 at 02:41:11PM +0200, Arnd Bergmann wrote: > > > On Thu, May 14, 2020 at 1:18 PM afzal mohammed wrote: > > > > It's clearly possible to do something very similar for older chips > > > (v6 or v7 without LPAE, possibly even v5), it just gets harder > > > while providing less benefit. > > > > Forget about doing this for anything without a PIPT cache - or you're > > going to end up having to flush the data cache each time you enter or > > exit the kernel. > > Right, let's forget I said anything about v5 or earlier ;-) > > I expected the non-aliasing VIPT caches to work the same as PIPT, can > you clarify if there is something to be aware of for those? I see that some > ARMv8 chips and most ARMv6 chips (not OMAP2 and Realview) are > of that kind, and at we clearly don't want to break running on ARMv8 at > least. There are some aliasing VIPT implementations on ARMv6, but I don't remember how common. > Anyway my point was that it's best to only do it for LPAE anyway, everything > else being a distraction, as the only non-LPAE SoCs I could find with > support for over 2GB are some of the higher-end i.MX6 versions and the > original highbank. Yep. -- RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTC broadband for 0.8mile line in suburbia: sync at 10.2Mbps down 587kbps up