Re: [PATCH v4 03/13] mips: Add MIPS Release 5 support

[Thomas Bogendoerfer <tsbogend@alpha.franken.de>]

On Thu, May 21, 2020 at 05:07:14PM +0300, Serge Semin wrote:
> There are five MIPS32/64 architecture releases currently available:
> from 1 to 6 except fourth one, which was intentionally skipped.
> Three of them can be called as major: 1st, 2nd and 6th, that not only
> have some system level alterations, but also introduced significant
> core/ISA level updates. The rest of the MIPS architecture releases are
> minor.
> 
> Even though they don't have as much ISA/system/core level changes
> as the major ones with respect to the previous releases, they still
> provide a set of updates (I'd say they were intended to be the
> intermediate releases before a major one) that might be useful for the
> kernel and user-level code, when activated by the kernel or compiler.
> In particular the following features were introduced or ended up being
> available at/after MIPS32/64 Release 5 architecture:
> + the last release of the misaligned memory access instructions,
> + virtualisation - VZ ASE - is optional component of the arch,
> + SIMD - MSA ASE - is optional component of the arch,
> + DSP ASE is optional component of the arch,
> + CP0.Status.FR=1 for CP1.FIR.F64=1 (pure 64-bit FPU general registers)
>   must be available if FPU is implemented,
> + CP1.FIR.Has2008 support is required so CP1.FCSR.{ABS2008,NAN2008} bits
>   are available.
> + UFR/UNFR aliases to access CP0.Status.FR from user-space by means of
>   ctc1/cfc1 instructions (enabled by CP0.Config5.UFR),
> + CP0.COnfig5.LLB=1 and eretnc instruction are implemented to without
>   accidentally clearing LL-bit when returning from an interrupt,
>   exception, or error trap,
> + XPA feature together with extended versions of CPx registers is
>   introduced, which needs to have mfhc0/mthc0 instructions available.
> 
> So due to these changes GNU GCC provides an extended instructions set
> support for MIPS32/64 Release 5 by default like eretnc/mfhc0/mthc0. Even
> though the architecture alteration isn't that big, it still worth to be
> taken into account by the kernel software. Finally we can't deny that
> some optimization/limitations might be found in future and implemented
> on some level in kernel or compiler. In this case having even
> intermediate MIPS architecture releases support would be more than
> useful.
> 
> So the most of the changes provided by this commit can be split into
> either compile- or runtime configs related. The compile-time related
> changes are caused by adding the new CONFIG_CPU_MIPS32_R5/CONFIG_CPU_MIPSR5
> configs and concern the code activating MIPSR2 or MIPSR6 already
> implemented features (like eretnc/LLbit, mthc0/mfhc0). In addition
> CPU_HAS_MSA can be now freely enabled for MIPS32/64 release 5 based
> platforms as this is done for CPU_MIPS32_R6 CPUs. The runtime changes
> concerns the features which are handled with respect to the MIPS ISA
> revision detected at run-time by means of CP0.Config.{AT,AR} bits. Alas
> these fields can be used to detect either r1 or r2 or r6 releases.
> But since we know which CPUs in fact support the R5 arch, we can manually
> set MIPS_CPU_ISA_M32R5/MIPS_CPU_ISA_M64R5 bit of c->isa_level and then
> use cpu_has_mips32r5/cpu_has_mips64r5 where it's appropriate.
> 
> Since XPA/EVA provide too complex alterationss and to have them used with
> MIPS32 Release 2 charged kernels (for compatibility with current platform
> configs) they are left to be setup as a separate kernel configs.
> 
> Co-developed-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Signed-off-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Cc: Paul Burton <paulburton@kernel.org>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: devicetree@vger.kernel.org
> ---
>  arch/mips/Kconfig                    | 56 +++++++++++++++++++++++++---
>  arch/mips/Makefile                   |  2 +
>  arch/mips/include/asm/asmmacro.h     | 18 +++++----
>  arch/mips/include/asm/compiler.h     |  5 +++
>  arch/mips/include/asm/cpu-features.h | 27 ++++++++++----
>  arch/mips/include/asm/cpu-info.h     |  2 +-
>  arch/mips/include/asm/cpu-type.h     |  7 +++-
>  arch/mips/include/asm/cpu.h          | 10 +++--
>  arch/mips/include/asm/fpu.h          |  4 +-
>  arch/mips/include/asm/hazards.h      |  8 ++--
>  arch/mips/include/asm/module.h       |  4 ++
>  arch/mips/include/asm/stackframe.h   |  2 +-
>  arch/mips/include/asm/switch_to.h    |  8 ++--
>  arch/mips/kernel/cpu-probe.c         | 17 +++++++++
>  arch/mips/kernel/entry.S             |  6 +--
>  arch/mips/kernel/proc.c              |  4 ++
>  arch/mips/kernel/r4k_fpu.S           | 14 +++----
>  arch/mips/kvm/vz.c                   |  6 +--
>  arch/mips/lib/csum_partial.S         |  6 ++-
>  arch/mips/mm/c-r4k.c                 |  7 ++--
>  arch/mips/mm/sc-mips.c               |  7 ++--
>  21 files changed, 163 insertions(+), 57 deletions(-)

applied to mips-next. I've changed the two /* fall through */ by fallthrough;
while appliny. Running checkpatch would have caught that ;-)

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]