From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1jcqkU-0000uD-Vv for mharc-grub-devel@gnu.org; Sun, 24 May 2020 09:33:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58998) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jcosI-00009x-SV for grub-devel@gnu.org; Sun, 24 May 2020 07:33:02 -0400 Received: from mail.kernel.org ([198.145.29.99]:40378) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jcosH-0004VU-Pm for grub-devel@gnu.org; Sun, 24 May 2020 07:33:02 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 468262076C; Sun, 24 May 2020 11:32:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1590319978; bh=Nr11XvY4B6ar+MWkAzNUkSQox75YdAagbkjoFb23RTQ=; h=From:To:Cc:Subject:Date:From; b=fTi7rgQSK3imj8jsFzZZzlmOGlcg96BwpuZ9L6W4VWjHmfAF0zagtYAxGPnYo4IM7 nIrnPuPIhbCOm2a63uiTky8hG1gY8cHo13YuFN2oqeWf/Uu9AzOBwg0wM6kjkhDdvt VMGsr69OeQ+oLc8vNVqcAC2yo8En8nw8VkccADqM= Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=why.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1jcosC-00EwfQ-5o; Sun, 24 May 2020 12:32:56 +0100 From: Marc Zyngier To: Vladimir Serbinenko Cc: grub-devel@gnu.org Subject: [PATCH] Fix 32-bit ARM handling of the CTR register Date: Sun, 24 May 2020 12:32:48 +0100 Message-Id: <20200524113248.367082-1-maz@kernel.org> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: phcoder@gmail.com, grub-devel@gnu.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Received-SPF: pass client-ip=198.145.29.99; envelope-from=maz@kernel.org; helo=mail.kernel.org X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/24 07:32:58 X-ACL-Warn: Detected OS = Linux 3.11 and newer X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-Mailman-Approved-At: Sun, 24 May 2020 09:33:05 -0400 X-BeenThere: grub-devel@gnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: The development of GNU GRUB List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 24 May 2020 11:33:03 -0000 When booting on an ARMv8 core that implements either CTR.IDC or CTR.DIC (indicating that some of the cache maintenance operations can be removed when dealing with I/D-cache coherency, GRUB dies with a "Unsupported cache type 0x........" message. This is pretty likely to happen when running in a virtual machine hosted on an arm64 machine (I've triggered it on a system built around a bunch of Cortex-A55 cores, which implements CTR.IDC). It turns out that the way GRUB deals with the CTR register is a bit harsh for anything from ARMv7 onwards. The layout of the register is backward compatible, meaning that nothing that gets added is allowed to break earlier behaviour. In this case, ignoring IDC is completely fine, and only results in unnecessary cache maintenance. We can thus avoid being paranoid, and align the 32bit behaviour with its 64bit equivalent. Signed-off-by: Marc Zyngier --- grub-core/kern/arm/cache.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/grub-core/kern/arm/cache.c b/grub-core/kern/arm/cache.c index af1c4bbf5..6c75193e4 100644 --- a/grub-core/kern/arm/cache.c +++ b/grub-core/kern/arm/cache.c @@ -93,13 +93,16 @@ probe_caches (void) grub_arch_cache_ilinesz = 8 << (cache_type & 3); type = ARCH_ARMV6; break; - case 0x80 ... 0x8f: + default: + /* + * The CTR register is pretty much unchanged from v7 onwards, + * and is guaranteed to be backward compatible (the IDC/DIC bits + * allow certain CMOs to be elided, but performing them is never + * wrong), hence handling it like its AArch64 equivalent. + */ grub_arch_cache_dlinesz = 4 << ((cache_type >> 16) & 0xf); grub_arch_cache_ilinesz = 4 << (cache_type & 0xf); type = ARCH_ARMV7; - break; - default: - grub_fatal ("Unsupported cache type 0x%x", cache_type); } if (grub_arch_cache_dlinesz > grub_arch_cache_ilinesz) grub_arch_cache_max_linesz = grub_arch_cache_dlinesz; -- 2.26.2