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From: kbuild test robot <lkp@intel.com>
To: kbuild-all@lists.01.org
Subject: [palmer:intc 8/18] arch/riscv/kernel/kgdb.c:47:5: warning: no previous prototype for 'decode_register_index'
Date: Fri, 29 May 2020 23:22:35 +0800	[thread overview]
Message-ID: <202005292332.UkOWwc2s%lkp@intel.com> (raw)

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tree:   https://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git intc
head:   2bd957e2b0b66894613a189939378cd1c000188d
commit: edde5584c7ab5d18b87f092fe6fe8a72590e7100 [8/18] riscv: Add SW single-step support for KDB
config: riscv-allyesconfig (attached as .config)
compiler: riscv64-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        git checkout edde5584c7ab5d18b87f092fe6fe8a72590e7100
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=riscv 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kbuild test robot <lkp@intel.com>

All warnings (new ones prefixed by >>, old ones prefixed by <<):

<<                  from arch/riscv/kernel/kgdb.c:9:
>> arch/riscv/kernel/kgdb.c:47:5: warning: no previous prototype for 'decode_register_index' [-Wmissing-prototypes]
47 | int decode_register_index(unsigned long opcode, int offset)
|     ^~~~~~~~~~~~~~~~~~~~~
<<                  from arch/riscv/kernel/kgdb.c:9:
>> arch/riscv/kernel/kgdb.c:52:5: warning: no previous prototype for 'decode_register_index_short' [-Wmissing-prototypes]
52 | int decode_register_index_short(unsigned long opcode, int offset)
|     ^~~~~~~~~~~~~~~~~~~~~~~~~~~
<<                  from arch/riscv/kernel/kgdb.c:9:
>> arch/riscv/kernel/kgdb.c:58:5: warning: no previous prototype for 'get_step_address' [-Wmissing-prototypes]
58 | int get_step_address(struct pt_regs *regs, unsigned long *next_addr)
|     ^~~~~~~~~~~~~~~~
arch/riscv/kernel/kgdb.c:139:5: warning: no previous prototype for 'do_single_step' [-Wmissing-prototypes]
139 | int do_single_step(struct pt_regs *regs)
|     ^~~~~~~~~~~~~~
arch/riscv/kernel/kgdb.c:276:6: warning: no previous prototype for 'kgdb_arch_handle_qxfer_pkt' [-Wmissing-prototypes]
276 | void kgdb_arch_handle_qxfer_pkt(char *remcom_in_buffer,
|      ^~~~~~~~~~~~~~~~~~~~~~~~~~
arch/riscv/kernel/kgdb.c:323:5: warning: no previous prototype for 'kgdb_riscv_kgdbbreak' [-Wmissing-prototypes]
323 | int kgdb_riscv_kgdbbreak(unsigned long addr)
|     ^~~~~~~~~~~~~~~~~~~~
In file included from arch/riscv/include/asm/kgdb.h:109,
from include/linux/kgdb.h:20,
from arch/riscv/kernel/kgdb.c:9:
arch/riscv/include/asm/gdb_xml.h:7:19: warning: 'riscv_gdb_stub_feature' defined but not used [-Wunused-const-variable=]
7 | static const char riscv_gdb_stub_feature[64] =
|                   ^~~~~~~~~~~~~~~~~~~~~~

vim +/decode_register_index +47 arch/riscv/kernel/kgdb.c

    46	
  > 47	int decode_register_index(unsigned long opcode, int offset)
    48	{
    49		return (opcode >> offset) & 0x1F;
    50	}
    51	
  > 52	int decode_register_index_short(unsigned long opcode, int offset)
    53	{
    54		return ((opcode >> offset) & 0x7) + 8;
    55	}
    56	
    57	/* Calculate the new address for after a step */
  > 58	int get_step_address(struct pt_regs *regs, unsigned long *next_addr)
    59	{
    60		unsigned long pc = regs->epc;
    61		unsigned long *regs_ptr = (unsigned long *)regs;
    62		unsigned int rs1_num, rs2_num;
    63		int op_code;
    64	
    65		if (probe_kernel_address((void *)pc, op_code))
    66			return -EINVAL;
    67		if ((op_code & __INSN_LENGTH_MASK) != __INSN_LENGTH_GE_32) {
    68			if (is_c_jalr_insn(op_code) || is_c_jr_insn(op_code)) {
    69				rs1_num = decode_register_index(op_code, RVC_C2_RS1_OPOFF);
    70				*next_addr = regs_ptr[rs1_num];
    71			} else if (is_c_j_insn(op_code) || is_c_jal_insn(op_code)) {
    72				*next_addr = EXTRACT_RVC_J_IMM(op_code) + pc;
    73			} else if (is_c_beqz_insn(op_code)) {
    74				rs1_num = decode_register_index_short(op_code,
    75								      RVC_C1_RS1_OPOFF);
    76				if (!rs1_num || regs_ptr[rs1_num] == 0)
    77					*next_addr = EXTRACT_RVC_B_IMM(op_code) + pc;
    78				else
    79					*next_addr = pc + 2;
    80			} else if (is_c_bnez_insn(op_code)) {
    81				rs1_num =
    82				    decode_register_index_short(op_code, RVC_C1_RS1_OPOFF);
    83				if (rs1_num && regs_ptr[rs1_num] != 0)
    84					*next_addr = EXTRACT_RVC_B_IMM(op_code) + pc;
    85				else
    86					*next_addr = pc + 2;
    87			} else {
    88				*next_addr = pc + 2;
    89			}
    90		} else {
    91			if ((op_code & __INSN_OPCODE_MASK) == __INSN_BRANCH_OPCODE) {
    92				bool result = false;
    93				long imm = EXTRACT_BTYPE_IMM(op_code);
    94				unsigned long rs1_val = 0, rs2_val = 0;
    95	
    96				rs1_num = decode_register_index(op_code, RVG_RS1_OPOFF);
    97				rs2_num = decode_register_index(op_code, RVG_RS2_OPOFF);
    98				if (rs1_num)
    99					rs1_val = regs_ptr[rs1_num];
   100				if (rs2_num)
   101					rs2_val = regs_ptr[rs2_num];
   102	
   103				if (is_beq_insn(op_code))
   104					result = (rs1_val == rs2_val) ? true : false;
   105				else if (is_bne_insn(op_code))
   106					result = (rs1_val != rs2_val) ? true : false;
   107				else if (is_blt_insn(op_code))
   108					result =
   109					    ((long)rs1_val <
   110					     (long)rs2_val) ? true : false;
   111				else if (is_bge_insn(op_code))
   112					result =
   113					    ((long)rs1_val >=
   114					     (long)rs2_val) ? true : false;
   115				else if (is_bltu_insn(op_code))
   116					result = (rs1_val < rs2_val) ? true : false;
   117				else if (is_bgeu_insn(op_code))
   118					result = (rs1_val >= rs2_val) ? true : false;
   119				if (result)
   120					*next_addr = imm + pc;
   121				else
   122					*next_addr = pc + 4;
   123			} else if (is_jal_insn(op_code)) {
   124				*next_addr = EXTRACT_JTYPE_IMM(op_code) + pc;
   125			} else if (is_jalr_insn(op_code)) {
   126				rs1_num = decode_register_index(op_code, RVG_RS1_OPOFF);
   127				if (rs1_num)
   128					*next_addr = ((unsigned long *)regs)[rs1_num];
   129				*next_addr += EXTRACT_ITYPE_IMM(op_code);
   130			} else if (is_sret_insn(op_code)) {
   131				*next_addr = pc;
   132			} else {
   133				*next_addr = pc + 4;
   134			}
   135		}
   136		return 0;
   137	}
   138	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org

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                 reply	other threads:[~2020-05-29 15:22 UTC|newest]

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