From: Vidya Sagar <vidyas@nvidia.com>
To: <jingoohan1@gmail.com>, <gustavo.pimentel@synopsys.com>,
<lorenzo.pieralisi@arm.com>, <bhelgaas@google.com>,
<amurray@thegoodpenguin.co.uk>, <robh@kernel.org>,
<thierry.reding@gmail.com>, <jonathanh@nvidia.com>
Cc: <linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<kthota@nvidia.com>, <mmaddireddy@nvidia.com>,
<vidyas@nvidia.com>, <sagar.tv@gmail.com>
Subject: [PATCH 1/2] PCI: dwc: Add support to handle prefetchable memory separately
Date: Tue, 2 Jun 2020 15:39:39 +0530 [thread overview]
Message-ID: <20200602100940.10575-2-vidyas@nvidia.com> (raw)
In-Reply-To: <20200602100940.10575-1-vidyas@nvidia.com>
Add required structure members to struct pcie_port to handle prefetchable
memory aperture separately from non-prefetchable memory aperture so that
any dependency on the order of their appearance in the 'ranges' property
of the respective PCIe device tree node can be removed.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
.../pci/controller/dwc/pcie-designware-host.c | 26 ++++++++++++-------
drivers/pci/controller/dwc/pcie-designware.h | 4 +++
2 files changed, 21 insertions(+), 9 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index 42fbfe2a1b8f..6f06d6bd9f00 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -363,13 +363,23 @@ int dw_pcie_host_init(struct pcie_port *pp)
pp->io_base = pci_pio_to_address(pp->io->start);
break;
case IORESOURCE_MEM:
- pp->mem = win->res;
- pp->mem->name = "MEM";
- mem_size = resource_size(pp->mem);
- if (upper_32_bits(mem_size))
- dev_warn(dev, "MEM resource size exceeds max for 32 bits\n");
- pp->mem_size = mem_size;
- pp->mem_bus_addr = pp->mem->start - win->offset;
+ if (win->res->flags & IORESOURCE_PREFETCH) {
+ pp->prefetch = win->res;
+ pp->prefetch->name = "PREFETCH";
+ pp->prefetch_base = pp->prefetch->start;
+ pp->prefetch_size = resource_size(pp->prefetch);
+ pp->perfetch_bus_addr = pp->prefetch->start -
+ win->offset;
+ } else {
+ pp->mem = win->res;
+ pp->mem->name = "MEM";
+ pp->mem_base = pp->mem->start;
+ mem_size = resource_size(pp->mem);
+ if (upper_32_bits(mem_size))
+ dev_warn(dev, "MEM resource size exceeds max for 32 bits\n");
+ pp->mem_size = mem_size;
+ pp->mem_bus_addr = pp->mem->start - win->offset;
+ }
break;
case 0:
pp->cfg = win->res;
@@ -394,8 +404,6 @@ int dw_pcie_host_init(struct pcie_port *pp)
}
}
- pp->mem_base = pp->mem->start;
-
if (!pp->va_cfg0_base) {
pp->va_cfg0_base = devm_pci_remap_cfgspace(dev,
pp->cfg0_base, pp->cfg0_size);
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 656e00f8fbeb..c87c1b2a1177 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -186,9 +186,13 @@ struct pcie_port {
u64 mem_base;
phys_addr_t mem_bus_addr;
u32 mem_size;
+ u64 prefetch_base;
+ phys_addr_t perfetch_bus_addr;
+ u64 prefetch_size;
struct resource *cfg;
struct resource *io;
struct resource *mem;
+ struct resource *prefetch;
struct resource *busn;
int irq;
const struct dw_pcie_host_ops *ops;
--
2.17.1
next prev parent reply other threads:[~2020-06-02 10:10 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-02 10:09 [PATCH 0/2] PCI: dwc: Add support to handle prefetchable memory separately Vidya Sagar
2020-06-02 10:09 ` Vidya Sagar [this message]
2020-07-29 18:56 ` [PATCH 1/2] " Rob Herring
2020-06-02 10:09 ` [PATCH 2/2] PCI: dwc: Use ATU region to map prefetchable memory region Vidya Sagar
2020-06-02 17:07 ` [PATCH 0/2] PCI: dwc: Add support to handle prefetchable memory separately Gustavo Pimentel
2020-06-17 18:56 ` Vidya Sagar
2020-06-17 21:14 ` Gustavo Pimentel
2020-07-06 4:35 ` Vidya Sagar
2020-09-07 17:10 ` Lorenzo Pieralisi
2020-10-05 12:19 ` Vidya Sagar
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