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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Matt Roper <matthew.d.roper@intel.com>
Cc: intel-gfx@lists.freedesktop.org,
	Lucas De Marchi <lucas.demarchi@intel.com>
Subject: Re: [Intel-gfx] [PATCH v3 05/15] drm/i915/rkl: Setup ports/phys
Date: Thu, 4 Jun 2020 20:09:14 +0300	[thread overview]
Message-ID: <20200604170914.GA6112@intel.com> (raw)
In-Reply-To: <20200603211529.3005059-6-matthew.d.roper@intel.com>

On Wed, Jun 03, 2020 at 02:15:19PM -0700, Matt Roper wrote:
> RKL uses DDI's A, B, TC1, and TC2 which need to map to combo PHY's A-D.
> 
> Bspec: 49181
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Aditya Swarup <aditya.swarup@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 34 ++++++++++++--------
>  drivers/gpu/drm/i915/i915_reg.h              |  4 ++-
>  2 files changed, 24 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index b4f8c88c779f..019fef8023ca 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7218,30 +7218,33 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
>  {
>  	if (phy == PHY_NONE)
>  		return false;
> -
> -	if (IS_ELKHARTLAKE(dev_priv))
> +	else if (IS_ROCKETLAKE(dev_priv))
> +		return phy <= PHY_D;

Or just 'return true' since combo PHYs is all we have.

/me weeps when looking at these functions.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> +	else if (IS_ELKHARTLAKE(dev_priv))
>  		return phy <= PHY_C;
> -
> -	if (INTEL_GEN(dev_priv) >= 11)
> +	else if (INTEL_GEN(dev_priv) >= 11)
>  		return phy <= PHY_B;
> -
> -	return false;
> +	else
> +		return false;
>  }
>  
>  bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
>  {
> -	if (INTEL_GEN(dev_priv) >= 12)
> +	if (IS_ROCKETLAKE(dev_priv))
> +		return false;
> +	else if (INTEL_GEN(dev_priv) >= 12)
>  		return phy >= PHY_D && phy <= PHY_I;
> -
> -	if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
> +	else if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
>  		return phy >= PHY_C && phy <= PHY_F;
> -
> -	return false;
> +	else
> +		return false;
>  }
>  
>  enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
>  {
> -	if (IS_ELKHARTLAKE(i915) && port == PORT_D)
> +	if (IS_ROCKETLAKE(i915) && port >= PORT_D)
> +		return (enum phy)port - 1;
> +	else if (IS_ELKHARTLAKE(i915) && port == PORT_D)
>  		return PHY_A;
>  
>  	return (enum phy)port;
> @@ -16829,7 +16832,12 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
>  	if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv))
>  		return;
>  
> -	if (INTEL_GEN(dev_priv) >= 12) {
> +	if (IS_ROCKETLAKE(dev_priv)) {
> +		intel_ddi_init(dev_priv, PORT_A);
> +		intel_ddi_init(dev_priv, PORT_B);
> +		intel_ddi_init(dev_priv, PORT_D);	/* DDI TC1 */
> +		intel_ddi_init(dev_priv, PORT_E);	/* DDI TC2 */
> +	} else if (INTEL_GEN(dev_priv) >= 12) {
>  		intel_ddi_init(dev_priv, PORT_A);
>  		intel_ddi_init(dev_priv, PORT_B);
>  		intel_ddi_init(dev_priv, PORT_D);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index db031269a05a..85137d268c4a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1869,9 +1869,11 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  #define _ICL_COMBOPHY_A			0x162000
>  #define _ICL_COMBOPHY_B			0x6C000
>  #define _EHL_COMBOPHY_C			0x160000
> +#define _RKL_COMBOPHY_D			0x161000
>  #define _ICL_COMBOPHY(phy)		_PICK(phy, _ICL_COMBOPHY_A, \
>  					      _ICL_COMBOPHY_B, \
> -					      _EHL_COMBOPHY_C)
> +					      _EHL_COMBOPHY_C, \
> +					      _RKL_COMBOPHY_D)
>  
>  /* CNL/ICL Port CL_DW registers */
>  #define _ICL_PORT_CL_DW(dw, phy)	(_ICL_COMBOPHY(phy) + \
> -- 
> 2.24.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2020-06-04 17:09 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-03 21:15 [Intel-gfx] [PATCH v3 00/15] Remaining RKL patches Matt Roper
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 01/15] drm/i915/rkl: Set transcoder mask properly Matt Roper
2020-06-04 15:34   ` Ville Syrjälä
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 02/15] drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2 Matt Roper
2020-06-03 22:34   ` Aditya Swarup
2020-06-03 23:12     ` Matt Roper
2020-06-04  1:18       ` Aditya Swarup
2020-06-04 17:01   ` Ville Syrjälä
2020-06-04 22:12     ` Matt Roper
2020-06-05 11:43       ` Ville Syrjälä
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 03/15] drm/i915/rkl: RKL has no MBUS_ABOX_CTL{1, 2} Matt Roper
2020-06-04 18:31   ` Ville Syrjälä
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 04/15] drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout Matt Roper
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 05/15] drm/i915/rkl: Setup ports/phys Matt Roper
2020-06-04 17:09   ` Ville Syrjälä [this message]
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 06/15] drm/i915/rkl: provide port/phy mapping for vbt Matt Roper
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 07/15] drm/i915/rkl: Update TGP's pin mapping when paired with RKL Matt Roper
2020-06-04 18:29   ` Ville Syrjälä
2020-06-04 23:18     ` Matt Roper
2020-06-05 11:52       ` Ville Syrjälä
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 08/15] drm/i915/rkl: Add DDC pin mapping Matt Roper
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 09/15] drm/i915/rkl: Don't try to access transcoder D Matt Roper
2020-06-04 16:55   ` Ville Syrjälä
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 10/15] drm/i915/rkl: Don't try to read out DSI transcoders Matt Roper
2020-06-04 16:59   ` Ville Syrjälä
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 11/15] drm/i915/rkl: Handle comp master/slave relationships for PHYs Matt Roper
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 12/15] drm/i915/rkl: Add DPLL4 support Matt Roper
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 13/15] drm/i915/rkl: Handle HTI Matt Roper
2020-06-04 16:59   ` Ville Syrjälä
2020-06-04 22:55     ` Matt Roper
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 14/15] drm/i915/rkl: Disable PSR2 Matt Roper
2020-06-04 17:41   ` Rodrigo Vivi
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 15/15] drm/i915/rkl: Add initial workarounds Matt Roper
2020-06-03 22:02 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Remaining RKL patches Patchwork
2020-06-03 22:03 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-06-03 22:23 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-06-04  8:34 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-06-04 16:39   ` Matt Roper
2020-06-05 22:11     ` Chris Wilson
2020-06-06  3:21       ` Matt Roper
2020-06-06  9:01         ` Chris Wilson

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