From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0AC3BC433E0 for ; Thu, 11 Jun 2020 15:40:00 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DEEBC206DC for ; Thu, 11 Jun 2020 15:39:59 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DEEBC206DC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7FE456E2EF; Thu, 11 Jun 2020 15:39:59 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 029EF6E2EF for ; Thu, 11 Jun 2020 15:39:58 +0000 (UTC) IronPort-SDR: y/OL264YxA9K05ByJXv43TExZmPBNLh7yyAMG6D8FPatBcX8EfTBvkNpiAyh4+ZGY//zllyljF NSE4mWO6TQhQ== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jun 2020 08:39:58 -0700 IronPort-SDR: jcrKcsnSFxz5N50vmJfHbUqSq2SgsVX5NeUslfAwOm9c6w3BC3DrhdHWQLH4CTBSfTqwS8tFFw vjFRYGVWjIqQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,499,1583222400"; d="scan'208";a="314845301" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by FMSMGA003.fm.intel.com with SMTP; 11 Jun 2020 08:39:56 -0700 Received: by stinkbox (sSMTP sendmail emulation); Thu, 11 Jun 2020 18:39:55 +0300 Date: Thu, 11 Jun 2020 18:39:55 +0300 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Imre Deak Message-ID: <20200611153955.GA6112@intel.com> References: <20200610183132.13341-1-imre.deak@intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200610183132.13341-1-imre.deak@intel.com> X-Patchwork-Hint: comment User-Agent: Mutt/1.10.1 (2018-07-13) Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915/tgl+: Fix DP MST ACT status handling X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Wed, Jun 10, 2020 at 09:31:31PM +0300, Imre Deak wrote: > On TGL+ the master transcoder's DP_TP_STATUS register should be used for > the MST ACT status handling, so make sure we do that even in case of > mulitple streams. > = > This fixes an ACT timeout problem during disabling when using multiple > streams. Not sure why this was not a problem during enabling (even the > slave's DP_TP_STATUS signaled ACT correctly), but following the spec > works in that case too, so let's do that. > = > There is one more place using DP_TP_STATUS, FEC enabling, but I haven't > found in BSpec which register to use in that case, so I leave the > clarification of that for later. > = > BSpec: 49190 > = > Signed-off-by: Imre Deak > --- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 47 +++++++++++++++++---- > 1 file changed, 39 insertions(+), 8 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/dr= m/i915/display/intel_dp_mst.c > index d18b406f2a7d..1c3654a117a9 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -316,6 +316,40 @@ intel_dp_mst_atomic_check(struct drm_connector *conn= ector, > return ret; > } > = > +static i915_reg_t > +master_dp_tp_status_reg(const struct intel_crtc_state *crtc_state, > + const struct intel_dp *intel_dp) > +{ > + struct drm_i915_private *dev_priv =3D to_i915(crtc_state->uapi.crtc->de= v); > + > + if (INTEL_GEN(dev_priv) >=3D 12) > + return TGL_DP_TP_STATUS(crtc_state->mst_master_transcoder); > + > + return intel_dp->regs.dp_tp_status; > +} > + > +static void clear_act_sent(const struct intel_crtc_state *crtc_state, > + const struct intel_dp *intel_dp) > +{ > + struct drm_i915_private *i915 =3D to_i915(crtc_state->uapi.crtc->dev); > + i915_reg_t dp_tp_status_reg =3D > + master_dp_tp_status_reg(crtc_state, intel_dp); > + > + intel_de_write(i915, dp_tp_status_reg, > + intel_de_read(i915, dp_tp_status_reg)); Followup material: Should we actually just clear the bit(s) we care about? No idea what other stuff is in there. > +} > + > +static bool wait_for_act_sent(const struct intel_crtc_state *crtc_state, > + const struct intel_dp *intel_dp) > +{ > + struct drm_i915_private *i915 =3D to_i915(crtc_state->uapi.crtc->dev); > + i915_reg_t dp_tp_status_reg =3D > + master_dp_tp_status_reg(crtc_state, intel_dp); > + > + return intel_de_wait_for_set(i915, dp_tp_status_reg, > + DP_TP_STATUS_ACT_SENT, 1) =3D=3D 0; > +} > + > static void intel_mst_disable_dp(struct intel_atomic_state *state, > struct intel_encoder *encoder, > const struct intel_crtc_state *old_crtc_state, > @@ -376,8 +410,7 @@ static void intel_mst_post_disable_dp(struct intel_at= omic_state *state, > TRANS_DDI_FUNC_CTL(old_crtc_state->cpu_transcoder), > val); > = > - if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status, > - DP_TP_STATUS_ACT_SENT, 1)) > + if (!wait_for_act_sent(old_crtc_state, intel_dp)) > drm_err(&dev_priv->drm, > "Timed out waiting for ACT sent when disabling\n"); > drm_dp_check_act_status(&intel_dp->mst_mgr); > @@ -443,7 +476,6 @@ static void intel_mst_pre_enable_dp(struct intel_atom= ic_state *state, > struct intel_connector *connector =3D > to_intel_connector(conn_state->connector); > int ret; > - u32 temp; > bool first_mst_stream; > = > /* MST encoders are bound to a crtc, not to a connector, > @@ -476,8 +508,8 @@ static void intel_mst_pre_enable_dp(struct intel_atom= ic_state *state, > drm_err(&dev_priv->drm, "failed to allocate vcpi\n"); > = > intel_dp->active_mst_links++; > - temp =3D intel_de_read(dev_priv, intel_dp->regs.dp_tp_status); > - intel_de_write(dev_priv, intel_dp->regs.dp_tp_status, temp); > + > + clear_act_sent(pipe_config, intel_dp); > = > ret =3D drm_dp_update_payload_part1(&intel_dp->mst_mgr); > = > @@ -513,9 +545,8 @@ static void intel_mst_enable_dp(struct intel_atomic_s= tate *state, > drm_dbg_kms(&dev_priv->drm, "active links %d\n", > intel_dp->active_mst_links); > = > - if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status, > - DP_TP_STATUS_ACT_SENT, 1)) > - drm_err(&dev_priv->drm, "Timed out waiting for ACT sent\n"); > + if (!wait_for_act_sent(pipe_config, intel_dp)) > + drm_err(&dev_priv->drm, "Timed out waiting for ACT sent when enabling\= n"); > = > drm_dp_check_act_status(&intel_dp->mst_mgr); > = > -- = > 2.23.1 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx