From: Sasha Levin <sashal@kernel.org>
To: gregkh@linuxfoundation.org
Cc: pbonzini@redhat.com, stable@vger.kernel.org
Subject: Re: FAILED: patch "[PATCH] KVM: x86: only do L1TF workaround on affected processors" failed to apply to 4.19-stable tree
Date: Mon, 15 Jun 2020 13:13:08 -0400 [thread overview]
Message-ID: <20200615171308.GF5492@sasha-vm> (raw)
In-Reply-To: <159222779021249@kroah.com>
On Mon, Jun 15, 2020 at 03:29:50PM +0200, gregkh@linuxfoundation.org wrote:
>
>The patch below does not apply to the 4.19-stable tree.
>If someone wants it applied there, or to any other stable or longterm
>tree, then please email the backport, including the original git commit
>id to <stable@vger.kernel.org>.
>
>thanks,
>
>greg k-h
>
>------------------ original commit in Linus's tree ------------------
>
>From d43e2675e96fc6ae1a633b6a69d296394448cc32 Mon Sep 17 00:00:00 2001
>From: Paolo Bonzini <pbonzini@redhat.com>
>Date: Tue, 19 May 2020 05:34:41 -0400
>Subject: [PATCH] KVM: x86: only do L1TF workaround on affected processors
>
>KVM stores the gfn in MMIO SPTEs as a caching optimization. These are split
>in two parts, as in "[high 11111 low]", to thwart any attempt to use these bits
>in an L1TF attack. This works as long as there are 5 free bits between
>MAXPHYADDR and bit 50 (inclusive), leaving bit 51 free so that the MMIO
>access triggers a reserved-bit-set page fault.
>
>The bit positions however were computed wrongly for AMD processors that have
>encryption support. In this case, x86_phys_bits is reduced (for example
>from 48 to 43, to account for the C bit at position 47 and four bits used
>internally to store the SEV ASID and other stuff) while x86_cache_bits in
>would remain set to 48, and _all_ bits between the reduced MAXPHYADDR
>and bit 51 are set. Then low_phys_bits would also cover some of the
>bits that are set in the shadow_mmio_value, terribly confusing the gfn
>caching mechanism.
>
>To fix this, avoid splitting gfns as long as the processor does not have
>the L1TF bug (which includes all AMD processors). When there is no
>splitting, low_phys_bits can be set to the reduced MAXPHYADDR removing
>the overlap. This fixes "npt=0" operation on EPYC processors.
>
>Thanks to Maxim Levitsky for bisecting this bug.
>
>Cc: stable@vger.kernel.org
>Fixes: 52918ed5fcf0 ("KVM: SVM: Override default MMIO mask if memory encryption is enabled")
>Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
I took these two additional patches for 4.14 and 4.19:
26c44a63a291 ("KVM: x86/mmu: Consolidate "is MMIO SPTE" code")
21dd7466353c ("kvm: x86: Fix L1TF mitigation for shadow MMU")
--
Thanks,
Sasha
prev parent reply other threads:[~2020-06-15 17:13 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-15 13:29 FAILED: patch "[PATCH] KVM: x86: only do L1TF workaround on affected processors" failed to apply to 4.19-stable tree gregkh
2020-06-15 17:13 ` Sasha Levin [this message]
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