From: Imre Deak <imre.deak@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v2 1/6] drm/i915/tgl+: Use the correct DP_TP_* register instances in MST encoders
Date: Wed, 17 Jun 2020 00:11:44 +0300 [thread overview]
Message-ID: <20200616211146.23027-1-imre.deak@intel.com> (raw)
In-Reply-To: <20200616141855.746-1-imre.deak@intel.com>
MST encoders must use the master MST transcoder's DP_TP_STATUS and
DP_TP_CONTROL registers. Atm, during the HW readout of an MST encoder
connected to a slave transcoder we reset these register addresses in
intel_dp::regs.dp_tp_* to the slave transcoder's DP_TP_* register
addresses incorrectly; fix this.
One example where the above overwite happens is the encoder HW state
validation after enabling multiple streams; see
intel_dp_mst_enc_get_config(). After that during disabling any stream
we'll get a
'Timed out waiting for ACT sent when disabling'
error, due to reading from the incorrect DP_TP_STATUS register.
This change replaces
https://patchwork.freedesktop.org/patch/369577/?series=78193&rev=1
which just papered over the problem.
v2:
- Correct the failure scenario in the commit log. (José)
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 15 ++++++++++-----
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index ca7bb2294d2b..73d6cc29291a 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4193,11 +4193,6 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)))
return;
- if (INTEL_GEN(dev_priv) >= 12) {
- intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(cpu_transcoder);
- intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(cpu_transcoder);
- }
-
intel_dsc_get_config(encoder, pipe_config);
temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
@@ -4299,6 +4294,16 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
break;
}
+ if (INTEL_GEN(dev_priv) >= 12) {
+ enum transcoder transcoder =
+ intel_dp_mst_is_slave_trans(pipe_config) ?
+ pipe_config->mst_master_transcoder :
+ pipe_config->cpu_transcoder;
+
+ intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder);
+ intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder);
+ }
+
pipe_config->has_audio =
intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
--
2.23.1
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next prev parent reply other threads:[~2020-06-16 21:11 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-16 14:18 [Intel-gfx] [PATCH 1/6] drm/i915/tgl+: Use the correct DP_TP_* register instances in MST encoders Imre Deak
2020-06-16 14:18 ` [Intel-gfx] [PATCH 2/6] drm/i915/dp_mst: Disable link training fallback on MST links Imre Deak
2020-06-16 15:22 ` Ville Syrjälä
2020-06-16 15:30 ` Imre Deak
2020-06-16 15:39 ` Ville Syrjälä
2020-06-16 15:49 ` Imre Deak
2020-06-16 16:20 ` Ville Syrjälä
2020-06-16 21:11 ` [Intel-gfx] [PATCH v2 " Imre Deak
2020-06-16 14:18 ` [Intel-gfx] [PATCH 3/6] drm/i915/dp_mst: Move clearing the ACT sent flag closer to its polling Imre Deak
2020-06-16 15:47 ` Ville Syrjälä
2020-06-16 14:18 ` [Intel-gfx] [PATCH 4/6] drm/i915/dp_mst: Clear only the ACT sent flag from DP_TP_STATUS Imre Deak
2020-06-16 15:47 ` Ville Syrjälä
2020-06-16 14:18 ` [Intel-gfx] [PATCH 5/6] drm/i915/dp_mst: Clear the ACT sent flag during encoder disabling too Imre Deak
2020-06-16 15:47 ` Ville Syrjälä
2020-06-16 14:18 ` [PATCH 6/6] drm/i915/dp_mst: Ensure the DPCD ACT sent flag is cleared before waiting for it Imre Deak
2020-06-16 14:18 ` [Intel-gfx] " Imre Deak
2020-06-16 15:45 ` Ville Syrjälä
2020-06-16 15:45 ` [Intel-gfx] " Ville Syrjälä
2020-06-16 15:54 ` Imre Deak
2020-06-16 15:54 ` [Intel-gfx] " Imre Deak
2020-06-16 16:23 ` Ville Syrjälä
2020-06-16 16:23 ` [Intel-gfx] " Ville Syrjälä
2020-06-16 16:40 ` Ville Syrjälä
2020-06-16 16:40 ` [Intel-gfx] " Ville Syrjälä
2020-06-16 16:47 ` Imre Deak
2020-06-16 16:47 ` [Intel-gfx] " Imre Deak
2020-06-16 21:11 ` [PATCH v2 " Imre Deak
2020-06-16 21:11 ` [Intel-gfx] " Imre Deak
2020-06-17 15:27 ` Lyude Paul
2020-06-17 15:27 ` [Intel-gfx] " Lyude Paul
2020-06-23 7:30 ` Imre Deak
2020-06-23 7:30 ` [Intel-gfx] " Imre Deak
2020-06-16 15:46 ` [Intel-gfx] [PATCH 1/6] drm/i915/tgl+: Use the correct DP_TP_* register instances in MST encoders Ville Syrjälä
2020-06-16 16:32 ` Souza, Jose
2020-06-16 16:42 ` Imre Deak
2020-06-16 17:02 ` Souza, Jose
2020-06-16 17:32 ` Imre Deak
2020-06-16 19:50 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/6] " Patchwork
2020-06-16 21:11 ` Imre Deak [this message]
2020-06-16 22:38 ` [Intel-gfx] [PATCH v2 1/6] " Souza, Jose
2020-06-16 22:16 ` [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/6] " Patchwork
2020-06-23 7:21 ` Imre Deak
2020-06-16 23:36 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/6] drm/i915/tgl+: Use the correct DP_TP_* register instances in MST encoders (rev4) Patchwork
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