From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35741C433E0 for ; Fri, 19 Jun 2020 15:24:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0B8CC21582 for ; Fri, 19 Jun 2020 15:24:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1592580270; bh=TT+8tMvqgygFxoAAc7BZuKJHREEz6edhkE6V6E4qA9c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=QMmgClBX+gLZ6you+K/dT55sNHPdDZcgYd1Q5B973KC8rpxVJG5RWIOfFaSHZ5NOP tQoNMG6w0wrZj7xk0OaCJhQCrqEKMoIA1FIv2ZqwpoALokiIxeJRld66ucGTP0/dQf q/KssTw0ZvBT9GYsnOWSfpQaHL1dlD7GbDiKW5Us= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2392007AbgFSPY2 (ORCPT ); Fri, 19 Jun 2020 11:24:28 -0400 Received: from mail.kernel.org ([198.145.29.99]:52470 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2392816AbgFSPVK (ORCPT ); Fri, 19 Jun 2020 11:21:10 -0400 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 9E98820706; Fri, 19 Jun 2020 15:21:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1592580069; bh=TT+8tMvqgygFxoAAc7BZuKJHREEz6edhkE6V6E4qA9c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hsB71NIVvx+wj1pPqoH7LL79corNFDEtzkBP/1ZZnnew6OMidOHECrheD0Fr7stpH Fo1OigMBVi15ZCErYzcLMKSPwHYyDyX8f/n44qegoV8pHBg5TE9cHAdXS1v4zYf3lm 35sRg+Kog1IEBBjz9YbcOny2h9jwAEaehfThi0lc= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Paul Hsieh , Eric Yang , Rodrigo Siqueira , Alex Deucher , Sasha Levin Subject: [PATCH 5.7 109/376] drm/amd/display: dmcu wait loop calculation is incorrect in RV Date: Fri, 19 Jun 2020 16:30:27 +0200 Message-Id: <20200619141715.506669577@linuxfoundation.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200619141710.350494719@linuxfoundation.org> References: <20200619141710.350494719@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Paul Hsieh [ Upstream commit 7fc5c319efceaed1a23b7ef35c333553ce39fecf ] [Why] Driver already get display clock from SMU base on MHz, but driver read again and mutiple 1000 cause wait loop value is overflow. [How] remove coding error Signed-off-by: Paul Hsieh Reviewed-by: Eric Yang Acked-by: Rodrigo Siqueira Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- .../drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c index 97b7f32294fd..c320b7af7d34 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c @@ -97,9 +97,6 @@ int rv1_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_di VBIOSSMC_MSG_SetDispclkFreq, requested_dispclk_khz / 1000); - /* Actual dispclk set is returned in the parameter register */ - actual_dispclk_set_mhz = REG_READ(MP1_SMN_C2PMSG_83) * 1000; - if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) { if (clk_mgr->dfs_bypass_disp_clk != actual_dispclk_set_mhz) -- 2.25.1