From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.5 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37412C433DF for ; Fri, 3 Jul 2020 11:38:57 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1271B20772 for ; Fri, 3 Jul 2020 11:38:56 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1271B20772 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9D3516E34E; Fri, 3 Jul 2020 11:38:56 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id A63306E34E for ; Fri, 3 Jul 2020 11:38:55 +0000 (UTC) IronPort-SDR: x3JryPzbfBfLA7x9HUeIWDT5YIebU4hdWaI3XA7G5KwkG8YWduVdwXbGzoOgMrPnmRKJ4UU97c qItbzqoMKkbQ== X-IronPort-AV: E=McAfee;i="6000,8403,9670"; a="127229483" X-IronPort-AV: E=Sophos;i="5.75,308,1589266800"; d="scan'208";a="127229483" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jul 2020 04:38:55 -0700 IronPort-SDR: iR5H8Kye538OkL9TskPvWD5B1SjARUC1urySpkbjoGGrOizVuN5aDmAXt4AJYk/MjL7DqrjrRG AlHACXYnyhCA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,308,1589266800"; d="scan'208";a="322395927" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by orsmga007.jf.intel.com with SMTP; 03 Jul 2020 04:38:53 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 03 Jul 2020 14:38:52 +0300 Date: Fri, 3 Jul 2020 14:38:52 +0300 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: "Souza, Jose" Message-ID: <20200703113852.GL6112@intel.com> References: <20200702153723.24327-1-ville.syrjala@linux.intel.com> <20200702153723.24327-2-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-Patchwork-Hint: comment User-Agent: Mutt/1.10.1 (2018-07-13) Subject: Re: [Intel-gfx] [PATCH 1/4] drm/i915/fbc: Use the correct plane stride X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "intel-gfx@lists.freedesktop.org" Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Thu, Jul 02, 2020 at 11:24:04PM +0000, Souza, Jose wrote: > On Thu, 2020-07-02 at 18:37 +0300, Ville Syrjala wrote: > > From: Ville Syrj=E4l=E4 > > = > > Consult the actual plane stride instead of the fb stride. The two > > will disagree when we remap the gtt. The plane stride is what the > > hw will be fed so that's what we should look at for the FBC > > retrictions/cfb allocation. > > = > > Since we no longer require a fence we are going to attempt using > > FBC with remapping, and so we should look at correct stride. > > = > > With 90/270 degree rotation the plane stride is stored in units > > of pixels, so we need to conver it to bytes for the purposes > > of calculating the cfb stride. Not entirely sure if this matches > > the hw behaviour though. Need to reverse engineer that at some > > point... > > = > > We also need to reorder the pixel format check vs. stride check > > to avoid triggering a spurious WARN(stride & 63) with cpp=3D=3D1 and > > plane stride=3D=3D32. > > = > > v2: Try to deal with rotated stride and related WARN > > = > = > Reviewed-by: Jos=E9 Roberto de Souza > = > > Cc: Jos=E9 Roberto de Souza > > Fixes: 691f7ba58d52 ("drm/i915/display/fbc: Make fences a nice-to-have = for GEN9+") > > Signed-off-by: Ville Syrj=E4l=E4 > > --- > > drivers/gpu/drm/i915/display/intel_fbc.c | 16 ++++++++++------ > > 1 file changed, 10 insertions(+), 6 deletions(-) > > = > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm= /i915/display/intel_fbc.c > > index 69a0682ddb6a..d30c2a389294 100644 > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c > > @@ -695,9 +695,13 @@ static void intel_fbc_update_state_cache(struct in= tel_crtc *crtc, > > cache->plane.pixel_blend_mode =3D plane_state->hw.pixel_blend_mode; > > = > > cache->fb.format =3D fb->format; > > - cache->fb.stride =3D fb->pitches[0]; > > cache->fb.modifier =3D fb->modifier; > > = > > + /* FIXME is this correct? */ > > + cache->fb.stride =3D plane_state->color_plane[0].stride; > > + if (drm_rotation_90_or_270(plane_state->hw.rotation)) > = > If it was wrong our CI would caught this in BDW or SNB for example. Not really. Well, certainly not on pre-skl since they don't do 90/270 rotation. And probably not even on skl+ since any wrong assumption about how the cfb stride is calculated by the hw would just cause it to scribble over stolen memory we didn't allocate. So unless we've started to use stolen more extensively in recent times such problems would probably go unnoticed. > = > > + cache->fb.stride *=3D fb->format->cpp[0]; > > + > > /* FBC1 compression interval: arbitrary choice of 1 second */ > > cache->interval =3D drm_mode_vrefresh(&crtc_state->hw.adjusted_mode); > > = > > @@ -797,6 +801,11 @@ static bool intel_fbc_can_activate(struct intel_cr= tc *crtc) > > return false; > > } > > = > > + if (!pixel_format_is_valid(dev_priv, cache->fb.format->format)) { > > + fbc->no_fbc_reason =3D "pixel format is invalid"; > > + return false; > > + } > > + > > if (!rotation_is_valid(dev_priv, cache->fb.format->format, > > cache->plane.rotation)) { > > fbc->no_fbc_reason =3D "rotation unsupported"; > > @@ -813,11 +822,6 @@ static bool intel_fbc_can_activate(struct intel_cr= tc *crtc) > > return false; > > } > > = > > - if (!pixel_format_is_valid(dev_priv, cache->fb.format->format)) { > > - fbc->no_fbc_reason =3D "pixel format is invalid"; > > - return false; > > - } > > - > > if (cache->plane.pixel_blend_mode !=3D DRM_MODE_BLEND_PIXEL_NONE && > > cache->fb.format->has_alpha) { > > fbc->no_fbc_reason =3D "per-pixel alpha blending is incompatible wit= h FBC"; -- = Ville Syrj=E4l=E4 Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx