From: Peter Zijlstra <peterz@infradead.org>
To: kan.liang@linux.intel.com
Cc: mingo@redhat.com, acme@kernel.org, tglx@linutronix.de,
bp@alien8.de, x86@kernel.org, linux-kernel@vger.kernel.org,
mark.rutland@arm.com, alexander.shishkin@linux.intel.com,
jolsa@redhat.com, namhyung@kernel.org, dave.hansen@intel.com,
yu-cheng.yu@intel.com, bigeasy@linutronix.de, gorcunov@gmail.com,
hpa@zytor.com, alexey.budankov@linux.intel.com,
eranian@google.com, ak@linux.intel.com, like.xu@linux.intel.com,
yao.jin@linux.intel.com, wei.w.wang@intel.com
Subject: Re: [PATCH V3 00/23] Support Architectural LBR
Date: Fri, 3 Jul 2020 21:34:08 +0200 [thread overview]
Message-ID: <20200703193408.GH2483@worktop.programming.kicks-ass.net> (raw)
In-Reply-To: <1593780569-62993-1-git-send-email-kan.liang@linux.intel.com>
So far so good; I'll merge in these little changes.
I have one more question, but I'll reply for that seperately and we can
do that on top if so.
---
Index: linux-2.6/arch/x86/events/intel/lbr.c
===================================================================
--- linux-2.6.orig/arch/x86/events/intel/lbr.c
+++ linux-2.6/arch/x86/events/intel/lbr.c
@@ -411,7 +411,7 @@ static __always_inline u64 rdlbr_info(un
return val;
}
-static __always_inline void
+static inline void
wrlbr_all(struct lbr_entry *lbr, unsigned int idx, bool need_info)
{
wrlbr_from(idx, lbr->from);
@@ -420,7 +420,7 @@ wrlbr_all(struct lbr_entry *lbr, unsigne
wrlbr_info(idx, lbr->info);
}
-static __always_inline bool
+static inline bool
rdlbr_all(struct lbr_entry *lbr, unsigned int idx, bool need_info)
{
u64 from = rdlbr_from(idx, NULL);
Index: linux-2.6/arch/x86/events/perf_event.h
===================================================================
--- linux-2.6.orig/arch/x86/events/perf_event.h
+++ linux-2.6/arch/x86/events/perf_event.h
@@ -775,7 +775,7 @@ struct x86_perf_task_context {
struct x86_perf_task_context_arch_lbr {
struct x86_perf_task_context_opt opt;
- struct lbr_entry entries[0];
+ struct lbr_entry entries[];
};
/*
@@ -787,17 +787,15 @@ struct x86_perf_task_context_arch_lbr {
* Do not put anything after the LBR state.
*/
struct x86_perf_task_context_arch_lbr_xsave {
- union {
- struct x86_perf_task_context_opt opt;
- u8 padding[64];
- };
+ struct x86_perf_task_context_opt opt;
+
union {
struct xregs_state xsave;
struct {
struct fxregs_state i387;
struct xstate_header header;
struct arch_lbr_state lbr;
- };
+ } __attribute__ ((packed, aligned (XSAVE_ALIGNMENT)));
};
};
Index: linux-2.6/arch/x86/include/asm/fpu/types.h
===================================================================
--- linux-2.6.orig/arch/x86/include/asm/fpu/types.h
+++ linux-2.6/arch/x86/include/asm/fpu/types.h
@@ -253,7 +253,7 @@ struct arch_lbr_state {
u64 ler_from;
u64 ler_to;
u64 ler_info;
- struct lbr_entry entries[0];
+ struct lbr_entry entries[];
} __packed;
struct xstate_header {
@@ -280,8 +280,8 @@ struct xstate_header {
struct xregs_state {
struct fxregs_state i387;
struct xstate_header header;
- u8 extended_state_area[0];
-} __attribute__ ((packed, aligned (64)));
+ u8 extended_state_area[];
+} __attribute__ ((packed, aligned (XSAVE_ALIGNMENT)));
/*
* This is a union of all the possible FPU state formats
Index: linux-2.6/arch/x86/include/asm/perf_event.h
===================================================================
--- linux-2.6.orig/arch/x86/include/asm/perf_event.h
+++ linux-2.6/arch/x86/include/asm/perf_event.h
@@ -283,7 +283,7 @@ struct pebs_xmm {
};
struct pebs_lbr {
- struct lbr_entry lbr[0]; /* Variable length */
+ struct lbr_entry lbr[]; /* Variable length */
};
/*
prev parent reply other threads:[~2020-07-03 19:34 UTC|newest]
Thread overview: 59+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-03 12:49 [PATCH V3 00/23] Support Architectural LBR kan.liang
2020-07-03 12:49 ` [PATCH V3 01/23] x86/cpufeatures: Add Architectural LBRs feature bit kan.liang
2020-07-08 9:51 ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-07-09 23:00 ` Dave Hansen
2020-07-10 9:51 ` Peter Zijlstra
2020-07-10 14:09 ` Liang, Kan
2020-07-03 12:49 ` [PATCH V3 02/23] perf/x86/intel/lbr: Add a function pointer for LBR reset kan.liang
2020-07-08 9:51 ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-07-03 12:49 ` [PATCH V3 03/23] perf/x86/intel/lbr: Add a function pointer for LBR read kan.liang
2020-07-08 9:51 ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-07-03 12:49 ` [PATCH V3 04/23] perf/x86/intel/lbr: Add the function pointers for LBR save and restore kan.liang
2020-07-08 9:51 ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-07-03 12:49 ` [PATCH V3 05/23] perf/x86/intel/lbr: Factor out a new struct for generic optimization kan.liang
2020-07-08 9:51 ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-07-03 12:49 ` [PATCH V3 06/23] perf/x86/intel/lbr: Use dynamic data structure for task_ctx kan.liang
2020-07-08 9:51 ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-07-03 12:49 ` [PATCH V3 07/23] x86/msr-index: Add bunch of MSRs for Arch LBR kan.liang
2020-07-08 9:51 ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-07-03 12:49 ` [PATCH V3 08/23] perf/x86: Expose CPUID enumeration bits for arch LBR kan.liang
2020-07-08 9:51 ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-07-03 12:49 ` [PATCH V3 09/23] perf/x86/intel/lbr: Support LBR_CTL kan.liang
2020-07-08 9:51 ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-07-03 12:49 ` [PATCH V3 10/23] perf/x86/intel/lbr: Unify the stored format of LBR information kan.liang
2020-07-08 9:51 ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-07-03 12:49 ` [PATCH V3 11/23] perf/x86/intel/lbr: Mark the {rd,wr}lbr_{to,from} wrappers __always_inline kan.liang
2020-07-08 9:51 ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-07-03 12:49 ` [PATCH V3 12/23] perf/x86/intel/lbr: Factor out rdlbr_all() and wrlbr_all() kan.liang
2020-07-08 9:51 ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-07-03 12:49 ` [PATCH V3 13/23] perf/x86/intel/lbr: Factor out intel_pmu_store_lbr kan.liang
2020-07-03 19:50 ` Peter Zijlstra
2020-07-03 20:59 ` Liang, Kan
2020-07-06 10:25 ` Peter Zijlstra
2020-07-06 13:32 ` Liang, Kan
2020-07-06 14:25 ` Peter Zijlstra
2020-07-06 22:29 ` Liang, Kan
2020-07-07 7:40 ` Peter Zijlstra
2020-07-08 9:51 ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-07-03 12:49 ` [PATCH V3 14/23] perf/x86/intel/lbr: Support Architectural LBR kan.liang
2020-07-08 9:51 ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-07-03 12:49 ` [PATCH V3 15/23] perf/core: Factor out functions to allocate/free the task_ctx_data kan.liang
2020-07-08 9:51 ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-07-03 12:49 ` [PATCH V3 16/23] perf/core: Use kmem_cache to allocate the PMU specific data kan.liang
2020-07-08 9:51 ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-07-03 12:49 ` [PATCH V3 17/23] perf/x86/intel/lbr: Create kmem_cache for the LBR context data kan.liang
2020-07-08 9:51 ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-07-03 12:49 ` [PATCH V3 18/23] perf/x86: Remove task_ctx_size kan.liang
2020-07-08 9:51 ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-07-03 12:49 ` [PATCH V3 19/23] x86/fpu: Use proper mask to replace full instruction mask kan.liang
2020-07-08 9:51 ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-07-03 12:49 ` [PATCH V3 20/23] x86/fpu/xstate: Support dynamic supervisor feature for LBR kan.liang
2020-07-08 9:51 ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-05-27 22:15 ` Thomas Gleixner
2020-07-03 12:49 ` [PATCH V3 21/23] x86/fpu/xstate: Add helpers for LBR dynamic supervisor feature kan.liang
2020-07-08 9:51 ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-07-03 12:49 ` [PATCH V3 22/23] perf/x86/intel/lbr: Support XSAVES/XRSTORS for LBR context switch kan.liang
2020-07-08 9:51 ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-07-03 12:49 ` [PATCH V3 23/23] perf/x86/intel/lbr: Support XSAVES for arch LBR read kan.liang
2020-07-08 9:51 ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-07-03 19:34 ` Peter Zijlstra [this message]
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