From: Max Filippov <jcmvbkbc@gmail.com>
To: qemu-devel@nongnu.org
Cc: "Max Filippov" <jcmvbkbc@gmail.com>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Peter Maydell" <peter.maydell@linaro.org>
Subject: [PATCH 01/21] softfloat: make NO_SIGNALING_NANS runtime property
Date: Mon, 6 Jul 2020 16:47:17 -0700 [thread overview]
Message-ID: <20200706234737.32378-2-jcmvbkbc@gmail.com> (raw)
In-Reply-To: <20200706234737.32378-1-jcmvbkbc@gmail.com>
target/xtensa, the only user of NO_SIGNALING_NANS macro has FPU
implementations with and without the corresponding property. With
NO_SIGNALING_NANS being a macro they cannot be a part of the same QEMU
executable.
Replace macro with new property in float_status to allow cores with
different FPU implementations coexist.
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: "Alex Bennée" <alex.bennee@linaro.org>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
fpu/softfloat-specialize.inc.c | 228 ++++++++++++++++----------------
include/fpu/softfloat-helpers.h | 5 +
include/fpu/softfloat-types.h | 1 +
3 files changed, 117 insertions(+), 117 deletions(-)
diff --git a/fpu/softfloat-specialize.inc.c b/fpu/softfloat-specialize.inc.c
index 44f5b661f831..b26bc039b0b6 100644
--- a/fpu/softfloat-specialize.inc.c
+++ b/fpu/softfloat-specialize.inc.c
@@ -79,13 +79,6 @@ this code that are retained.
* version 2 or later. See the COPYING file in the top-level directory.
*/
-/* Define for architectures which deviate from IEEE in not supporting
- * signaling NaNs (so all NaNs are treated as quiet).
- */
-#if defined(TARGET_XTENSA)
-#define NO_SIGNALING_NANS 1
-#endif
-
/* Define how the architecture discriminates signaling NaNs.
* This done with the most significant bit of the fraction.
* In IEEE 754-1985 this was implementation defined, but in IEEE 754-2008
@@ -111,12 +104,12 @@ static inline bool snan_bit_is_one(float_status *status)
static bool parts_is_snan_frac(uint64_t frac, float_status *status)
{
-#ifdef NO_SIGNALING_NANS
- return false;
-#else
- bool msb = extract64(frac, DECOMPOSED_BINARY_POINT - 1, 1);
- return msb == snan_bit_is_one(status);
-#endif
+ if (status->no_signaling_nans) {
+ return false;
+ } else {
+ bool msb = extract64(frac, DECOMPOSED_BINARY_POINT - 1, 1);
+ return msb == snan_bit_is_one(status);
+ }
}
/*----------------------------------------------------------------------------
@@ -170,9 +163,10 @@ static FloatParts parts_default_nan(float_status *status)
static FloatParts parts_silence_nan(FloatParts a, float_status *status)
{
-#ifdef NO_SIGNALING_NANS
- g_assert_not_reached();
-#elif defined(TARGET_HPPA)
+ if (status->no_signaling_nans) {
+ g_assert_not_reached();
+ }
+#if defined(TARGET_HPPA)
a.frac &= ~(1ULL << (DECOMPOSED_BINARY_POINT - 1));
a.frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 2);
#else
@@ -247,16 +241,16 @@ typedef struct {
bool float16_is_quiet_nan(float16 a_, float_status *status)
{
-#ifdef NO_SIGNALING_NANS
- return float16_is_any_nan(a_);
-#else
- uint16_t a = float16_val(a_);
- if (snan_bit_is_one(status)) {
- return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
+ if (status->no_signaling_nans) {
+ return float16_is_any_nan(a_);
} else {
- return ((a & ~0x8000) >= 0x7C80);
+ uint16_t a = float16_val(a_);
+ if (snan_bit_is_one(status)) {
+ return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
+ } else {
+ return ((a & ~0x8000) >= 0x7C80);
+ }
}
-#endif
}
/*----------------------------------------------------------------------------
@@ -266,16 +260,16 @@ bool float16_is_quiet_nan(float16 a_, float_status *status)
bool float16_is_signaling_nan(float16 a_, float_status *status)
{
-#ifdef NO_SIGNALING_NANS
- return 0;
-#else
- uint16_t a = float16_val(a_);
- if (snan_bit_is_one(status)) {
- return ((a & ~0x8000) >= 0x7C80);
+ if (status->no_signaling_nans) {
+ return 0;
} else {
- return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
+ uint16_t a = float16_val(a_);
+ if (snan_bit_is_one(status)) {
+ return ((a & ~0x8000) >= 0x7C80);
+ } else {
+ return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
+ }
}
-#endif
}
/*----------------------------------------------------------------------------
@@ -285,16 +279,16 @@ bool float16_is_signaling_nan(float16 a_, float_status *status)
bool float32_is_quiet_nan(float32 a_, float_status *status)
{
-#ifdef NO_SIGNALING_NANS
- return float32_is_any_nan(a_);
-#else
- uint32_t a = float32_val(a_);
- if (snan_bit_is_one(status)) {
- return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF);
+ if (status->no_signaling_nans) {
+ return float32_is_any_nan(a_);
} else {
- return ((uint32_t)(a << 1) >= 0xFF800000);
+ uint32_t a = float32_val(a_);
+ if (snan_bit_is_one(status)) {
+ return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF);
+ } else {
+ return ((uint32_t)(a << 1) >= 0xFF800000);
+ }
}
-#endif
}
/*----------------------------------------------------------------------------
@@ -304,16 +298,16 @@ bool float32_is_quiet_nan(float32 a_, float_status *status)
bool float32_is_signaling_nan(float32 a_, float_status *status)
{
-#ifdef NO_SIGNALING_NANS
- return 0;
-#else
- uint32_t a = float32_val(a_);
- if (snan_bit_is_one(status)) {
- return ((uint32_t)(a << 1) >= 0xFF800000);
+ if (status->no_signaling_nans) {
+ return 0;
} else {
- return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF);
+ uint32_t a = float32_val(a_);
+ if (snan_bit_is_one(status)) {
+ return ((uint32_t)(a << 1) >= 0xFF800000);
+ } else {
+ return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF);
+ }
}
-#endif
}
/*----------------------------------------------------------------------------
@@ -639,17 +633,17 @@ static float32 propagateFloat32NaN(float32 a, float32 b, float_status *status)
bool float64_is_quiet_nan(float64 a_, float_status *status)
{
-#ifdef NO_SIGNALING_NANS
- return float64_is_any_nan(a_);
-#else
- uint64_t a = float64_val(a_);
- if (snan_bit_is_one(status)) {
- return (((a >> 51) & 0xFFF) == 0xFFE)
- && (a & 0x0007FFFFFFFFFFFFULL);
+ if (status->no_signaling_nans) {
+ return float64_is_any_nan(a_);
} else {
- return ((a << 1) >= 0xFFF0000000000000ULL);
+ uint64_t a = float64_val(a_);
+ if (snan_bit_is_one(status)) {
+ return (((a >> 51) & 0xFFF) == 0xFFE)
+ && (a & 0x0007FFFFFFFFFFFFULL);
+ } else {
+ return ((a << 1) >= 0xFFF0000000000000ULL);
+ }
}
-#endif
}
/*----------------------------------------------------------------------------
@@ -659,17 +653,17 @@ bool float64_is_quiet_nan(float64 a_, float_status *status)
bool float64_is_signaling_nan(float64 a_, float_status *status)
{
-#ifdef NO_SIGNALING_NANS
- return 0;
-#else
- uint64_t a = float64_val(a_);
- if (snan_bit_is_one(status)) {
- return ((a << 1) >= 0xFFF0000000000000ULL);
+ if (status->no_signaling_nans) {
+ return 0;
} else {
- return (((a >> 51) & 0xFFF) == 0xFFE)
- && (a & UINT64_C(0x0007FFFFFFFFFFFF));
+ uint64_t a = float64_val(a_);
+ if (snan_bit_is_one(status)) {
+ return ((a << 1) >= 0xFFF0000000000000ULL);
+ } else {
+ return (((a >> 51) & 0xFFF) == 0xFFE)
+ && (a & UINT64_C(0x0007FFFFFFFFFFFF));
+ }
}
-#endif
}
/*----------------------------------------------------------------------------
@@ -778,21 +772,21 @@ static float64 propagateFloat64NaN(float64 a, float64 b, float_status *status)
int floatx80_is_quiet_nan(floatx80 a, float_status *status)
{
-#ifdef NO_SIGNALING_NANS
- return floatx80_is_any_nan(a);
-#else
- if (snan_bit_is_one(status)) {
- uint64_t aLow;
-
- aLow = a.low & ~0x4000000000000000ULL;
- return ((a.high & 0x7FFF) == 0x7FFF)
- && (aLow << 1)
- && (a.low == aLow);
+ if (status->no_signaling_nans) {
+ return floatx80_is_any_nan(a);
} else {
- return ((a.high & 0x7FFF) == 0x7FFF)
- && (UINT64_C(0x8000000000000000) <= ((uint64_t)(a.low << 1)));
+ if (snan_bit_is_one(status)) {
+ uint64_t aLow;
+
+ aLow = a.low & ~0x4000000000000000ULL;
+ return ((a.high & 0x7FFF) == 0x7FFF)
+ && (aLow << 1)
+ && (a.low == aLow);
+ } else {
+ return ((a.high & 0x7FFF) == 0x7FFF)
+ && (UINT64_C(0x8000000000000000) <= ((uint64_t)(a.low << 1)));
+ }
}
-#endif
}
/*----------------------------------------------------------------------------
@@ -803,21 +797,21 @@ int floatx80_is_quiet_nan(floatx80 a, float_status *status)
int floatx80_is_signaling_nan(floatx80 a, float_status *status)
{
-#ifdef NO_SIGNALING_NANS
- return 0;
-#else
- if (snan_bit_is_one(status)) {
- return ((a.high & 0x7FFF) == 0x7FFF)
- && ((a.low << 1) >= 0x8000000000000000ULL);
+ if (status->no_signaling_nans) {
+ return 0;
} else {
- uint64_t aLow;
+ if (snan_bit_is_one(status)) {
+ return ((a.high & 0x7FFF) == 0x7FFF)
+ && ((a.low << 1) >= 0x8000000000000000ULL);
+ } else {
+ uint64_t aLow;
- aLow = a.low & ~UINT64_C(0x4000000000000000);
- return ((a.high & 0x7FFF) == 0x7FFF)
- && (uint64_t)(aLow << 1)
- && (a.low == aLow);
+ aLow = a.low & ~UINT64_C(0x4000000000000000);
+ return ((a.high & 0x7FFF) == 0x7FFF)
+ && (uint64_t)(aLow << 1)
+ && (a.low == aLow);
+ }
}
-#endif
}
/*----------------------------------------------------------------------------
@@ -941,17 +935,17 @@ floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
bool float128_is_quiet_nan(float128 a, float_status *status)
{
-#ifdef NO_SIGNALING_NANS
- return float128_is_any_nan(a);
-#else
- if (snan_bit_is_one(status)) {
- return (((a.high >> 47) & 0xFFFF) == 0xFFFE)
- && (a.low || (a.high & 0x00007FFFFFFFFFFFULL));
+ if (status->no_signaling_nans) {
+ return float128_is_any_nan(a);
} else {
- return ((a.high << 1) >= 0xFFFF000000000000ULL)
- && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL));
+ if (snan_bit_is_one(status)) {
+ return (((a.high >> 47) & 0xFFFF) == 0xFFFE)
+ && (a.low || (a.high & 0x00007FFFFFFFFFFFULL));
+ } else {
+ return ((a.high << 1) >= 0xFFFF000000000000ULL)
+ && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL));
+ }
}
-#endif
}
/*----------------------------------------------------------------------------
@@ -961,17 +955,17 @@ bool float128_is_quiet_nan(float128 a, float_status *status)
bool float128_is_signaling_nan(float128 a, float_status *status)
{
-#ifdef NO_SIGNALING_NANS
- return 0;
-#else
- if (snan_bit_is_one(status)) {
- return ((a.high << 1) >= 0xFFFF000000000000ULL)
- && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL));
+ if (status->no_signaling_nans) {
+ return 0;
} else {
- return (((a.high >> 47) & 0xFFFF) == 0xFFFE)
- && (a.low || (a.high & UINT64_C(0x00007FFFFFFFFFFF)));
+ if (snan_bit_is_one(status)) {
+ return ((a.high << 1) >= 0xFFFF000000000000ULL)
+ && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL));
+ } else {
+ return (((a.high >> 47) & 0xFFFF) == 0xFFFE)
+ && (a.low || (a.high & UINT64_C(0x00007FFFFFFFFFFF)));
+ }
}
-#endif
}
/*----------------------------------------------------------------------------
@@ -981,16 +975,16 @@ bool float128_is_signaling_nan(float128 a, float_status *status)
float128 float128_silence_nan(float128 a, float_status *status)
{
-#ifdef NO_SIGNALING_NANS
- g_assert_not_reached();
-#else
- if (snan_bit_is_one(status)) {
- return float128_default_nan(status);
+ if (status->no_signaling_nans) {
+ g_assert_not_reached();
} else {
- a.high |= UINT64_C(0x0000800000000000);
- return a;
+ if (snan_bit_is_one(status)) {
+ return float128_default_nan(status);
+ } else {
+ a.high |= UINT64_C(0x0000800000000000);
+ return a;
+ }
}
-#endif
}
/*----------------------------------------------------------------------------
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
index 735ed6b653ee..e842f83a1285 100644
--- a/include/fpu/softfloat-helpers.h
+++ b/include/fpu/softfloat-helpers.h
@@ -95,6 +95,11 @@ static inline void set_snan_bit_is_one(bool val, float_status *status)
status->snan_bit_is_one = val;
}
+static inline void set_no_signaling_nans(bool val, float_status *status)
+{
+ status->no_signaling_nans = val;
+}
+
static inline bool get_float_detect_tininess(float_status *status)
{
return status->tininess_before_rounding;
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
index 7680193ebc1c..10bd208e559f 100644
--- a/include/fpu/softfloat-types.h
+++ b/include/fpu/softfloat-types.h
@@ -167,6 +167,7 @@ typedef struct float_status {
bool default_nan_mode;
/* not always used -- see snan_bit_is_one() in softfloat-specialize.h */
bool snan_bit_is_one;
+ bool no_signaling_nans;
} float_status;
#endif /* SOFTFLOAT_TYPES_H */
--
2.20.1
next prev parent reply other threads:[~2020-07-06 23:50 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-06 23:47 [PATCH 00/21] target/xtensa: implement double precision FPU Max Filippov
2020-07-06 23:47 ` Max Filippov [this message]
2020-07-07 10:28 ` [PATCH 01/21] softfloat: make NO_SIGNALING_NANS runtime property Alex Bennée
2020-07-08 17:41 ` Philippe Mathieu-Daudé
2020-07-06 23:47 ` [PATCH 02/21] softfloat: pass float_status pointer to pickNaN Max Filippov
2020-07-07 10:29 ` Alex Bennée
2020-07-06 23:47 ` [PATCH 03/21] softfloat: add xtensa specialization for pickNaNMulAdd Max Filippov
2020-07-07 10:29 ` Alex Bennée
2020-07-08 16:07 ` Richard Henderson
2020-07-08 18:11 ` Max Filippov
2020-07-06 23:47 ` [PATCH 04/21] target/xtensa: add geometry to xtensa_get_regfile_by_name Max Filippov
2020-07-06 23:47 ` [PATCH 05/21] target/xtensa: support copying registers up to 64 bits wide Max Filippov
2020-07-08 16:14 ` Richard Henderson
2020-07-08 17:14 ` Max Filippov
2020-07-06 23:47 ` [PATCH 06/21] target/xtensa: rename FPU2000 translators and helpers Max Filippov
2020-07-08 16:18 ` Richard Henderson
2020-07-06 23:47 ` [PATCH 07/21] target/xtensa: move FSR/FCR register accessors Max Filippov
2020-07-08 16:18 ` Richard Henderson
2020-07-06 23:47 ` [PATCH 08/21] target/xtensa: don't access BR regfile directly Max Filippov
2020-07-08 16:18 ` Richard Henderson
2020-07-06 23:47 ` [PATCH 09/21] target/xtensa: add DFP option, registers and opcodes Max Filippov
2020-07-08 16:25 ` Richard Henderson
2020-07-08 17:37 ` Max Filippov
2020-07-09 0:19 ` Richard Henderson
2020-07-09 5:14 ` Max Filippov
2020-07-06 23:47 ` [PATCH 10/21] target/xtensa: implement FPU division and square root Max Filippov
2020-07-06 23:47 ` [PATCH 11/21] tests/tcg/xtensa: fix test execution on ISS Max Filippov
2020-07-06 23:47 ` [PATCH 12/21] tests/tcg/xtensa: update test_fp0_arith for DFPU Max Filippov
2020-07-06 23:47 ` [PATCH 13/21] tests/tcg/xtensa: expand madd tests Max Filippov
2020-07-06 23:47 ` [PATCH 14/21] tests/tcg/xtensa: update test_fp0_conv for DFPU Max Filippov
2020-07-06 23:47 ` [PATCH 15/21] tests/tcg/xtensa: update test_fp1 " Max Filippov
2020-07-06 23:47 ` [PATCH 16/21] tests/tcg/xtensa: update test_lsc " Max Filippov
2020-07-06 23:47 ` [PATCH 17/21] tests/tcg/xtensa: add fp0 div and sqrt tests Max Filippov
2020-07-06 23:47 ` [PATCH 18/21] tests/tcg/xtensa: test double precision load/store Max Filippov
2020-07-06 23:47 ` [PATCH 19/21] tests/tcg/xtensa: add DFP0 arith tests Max Filippov
2020-07-06 23:47 ` [PATCH 20/21] target/xtensa: import DE_233L_FPU core Max Filippov
2020-07-06 23:47 ` [PATCH 21/21] target/xtensa: import DSP3400 core Max Filippov
2020-07-07 11:31 ` [PATCH 00/21] target/xtensa: implement double precision FPU Alex Bennée
2020-07-07 16:56 ` Max Filippov
2020-07-07 19:21 ` Alex Bennée
2020-07-07 23:14 ` Max Filippov
2020-07-08 8:50 ` Alex Bennée
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