From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5CDFC433E2 for ; Wed, 8 Jul 2020 11:09:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9AA6120739 for ; Wed, 8 Jul 2020 11:09:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728722AbgGHLJx (ORCPT ); Wed, 8 Jul 2020 07:09:53 -0400 Received: from elvis.franken.de ([193.175.24.41]:54232 "EHLO elvis.franken.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728701AbgGHLJw (ORCPT ); Wed, 8 Jul 2020 07:09:52 -0400 Received: from uucp (helo=alpha) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1jt7xS-0008Fx-00; Wed, 08 Jul 2020 13:09:46 +0200 Received: by alpha.franken.de (Postfix, from userid 1000) id C25CDC07D4; Wed, 8 Jul 2020 11:37:35 +0200 (CEST) Date: Wed, 8 Jul 2020 11:37:35 +0200 From: Thomas Bogendoerfer To: Huacai Chen Cc: linux-mips@vger.kernel.org, Fuxin Zhang , Zhangjin Wu , Huacai Chen , Jiaxun Yang Subject: Re: [PATCH] MIPS: Loongson64: Adjust IRQ layout Message-ID: <20200708093735.GD9458@alpha.franken.de> References: <1594030916-7520-1-git-send-email-chenhc@lemote.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1594030916-7520-1-git-send-email-chenhc@lemote.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org On Mon, Jul 06, 2020 at 06:21:56PM +0800, Huacai Chen wrote: > Adjust IRQ layout in order to use IRQ resources more efficiently, which > is done by adjusting NR_IRQS and MIPS_CPU_IRQ_BASE. > > Before this patch: > 0~15: ISA/LPC IRQs; > 16~55: Dynamic IRQs; > 56~63: MIPS CPU IRQs; > 64~127: PCH IRQs; > 128~255: Dynamic IRQs. > > After this patch: > 0~15: ISA/LPC IRQs; > 16~23: MIPS CPU IRQs; > 24~87: PCH IRQs; > 88~280: Dynamic IRQs. > > Signed-off-by: Huacai Chen > --- > arch/mips/include/asm/mach-loongson64/irq.h | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) applied to mips-next. Thomas. -- Crap can work. Given enough thrust pigs will fly, but it's not necessarily a good idea. [ RFC1925, 2.3 ]