From: Max Filippov <jcmvbkbc@gmail.com>
To: qemu-devel@nongnu.org
Cc: Max Filippov <jcmvbkbc@gmail.com>,
Richard Henderson <richard.henderson@linaro.org>
Subject: [PATCH v3 07/21] target/xtensa: move FSR/FCR register accessors
Date: Wed, 8 Jul 2020 15:20:47 -0700 [thread overview]
Message-ID: <20200708222101.24568-8-jcmvbkbc@gmail.com> (raw)
In-Reply-To: <20200708222101.24568-1-jcmvbkbc@gmail.com>
Move FSR/FCR register accessors from core opcodes to FPU2000 opcodes as
they are FPU2000-specific.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
target/xtensa/translate.c | 64 +++++++++++++++++++--------------------
1 file changed, 32 insertions(+), 32 deletions(-)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 0deaeef6b5fa..f859cd3f0818 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -2813,18 +2813,6 @@ static void translate_wur(DisasContext *dc, const OpcodeArg arg[],
tcg_gen_mov_i32(cpu_UR[par[0]], arg[0].in);
}
-static void translate_wur_fpu2k_fcr(DisasContext *dc, const OpcodeArg arg[],
- const uint32_t par[])
-{
- gen_helper_wur_fpu2k_fcr(cpu_env, arg[0].in);
-}
-
-static void translate_wur_fsr(DisasContext *dc, const OpcodeArg arg[],
- const uint32_t par[])
-{
- tcg_gen_andi_i32(cpu_UR[par[0]], arg[0].in, 0xffffff80);
-}
-
static void translate_xor(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
@@ -4665,16 +4653,6 @@ static const XtensaOpcodeOps core_ops[] = {
.name = "rur.expstate",
.translate = translate_rur,
.par = (const uint32_t[]){EXPSTATE},
- }, {
- .name = "rur.fcr",
- .translate = translate_rur,
- .par = (const uint32_t[]){FCR},
- .coprocessor = 0x1,
- }, {
- .name = "rur.fsr",
- .translate = translate_rur,
- .par = (const uint32_t[]){FSR},
- .coprocessor = 0x1,
}, {
.name = "rur.threadptr",
.translate = translate_rur,
@@ -5581,16 +5559,6 @@ static const XtensaOpcodeOps core_ops[] = {
.name = "wur.expstate",
.translate = translate_wur,
.par = (const uint32_t[]){EXPSTATE},
- }, {
- .name = "wur.fcr",
- .translate = translate_wur_fpu2k_fcr,
- .par = (const uint32_t[]){FCR},
- .coprocessor = 0x1,
- }, {
- .name = "wur.fsr",
- .translate = translate_wur_fsr,
- .par = (const uint32_t[]){FSR},
- .coprocessor = 0x1,
}, {
.name = "wur.threadptr",
.translate = translate_wur,
@@ -6510,6 +6478,18 @@ static void translate_wfr_s(DisasContext *dc, const OpcodeArg arg[],
tcg_gen_mov_i32(arg[0].out, arg[1].in);
}
+static void translate_wur_fpu2k_fcr(DisasContext *dc, const OpcodeArg arg[],
+ const uint32_t par[])
+{
+ gen_helper_wur_fpu2k_fcr(cpu_env, arg[0].in);
+}
+
+static void translate_wur_fpu2k_fsr(DisasContext *dc, const OpcodeArg arg[],
+ const uint32_t par[])
+{
+ tcg_gen_andi_i32(cpu_UR[par[0]], arg[0].in, 0xffffff80);
+}
+
static const XtensaOpcodeOps fpu2000_ops[] = {
{
.name = "abs.s",
@@ -6632,6 +6612,16 @@ static const XtensaOpcodeOps fpu2000_ops[] = {
.translate = translate_ftoi_s,
.par = (const uint32_t[]){float_round_nearest_even, false},
.coprocessor = 0x1,
+ }, {
+ .name = "rur.fcr",
+ .translate = translate_rur,
+ .par = (const uint32_t[]){FCR},
+ .coprocessor = 0x1,
+ }, {
+ .name = "rur.fsr",
+ .translate = translate_rur,
+ .par = (const uint32_t[]){FSR},
+ .coprocessor = 0x1,
}, {
.name = "ssi",
.translate = translate_ldsti,
@@ -6699,6 +6689,16 @@ static const XtensaOpcodeOps fpu2000_ops[] = {
.name = "wfr",
.translate = translate_wfr_s,
.coprocessor = 0x1,
+ }, {
+ .name = "wur.fcr",
+ .translate = translate_wur_fpu2k_fcr,
+ .par = (const uint32_t[]){FCR},
+ .coprocessor = 0x1,
+ }, {
+ .name = "wur.fsr",
+ .translate = translate_wur_fpu2k_fsr,
+ .par = (const uint32_t[]){FSR},
+ .coprocessor = 0x1,
},
};
--
2.20.1
next prev parent reply other threads:[~2020-07-08 22:42 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-08 22:20 [PATCH 00/21] target/xtensa: implement double precision FPU Max Filippov
2020-07-08 22:20 ` [PATCH v3 01/21] softfloat: make NO_SIGNALING_NANS runtime property Max Filippov
2020-07-08 23:54 ` Richard Henderson
2020-07-08 22:20 ` [PATCH v3 02/21] softfloat: pass float_status pointer to pickNaN Max Filippov
2020-07-08 23:59 ` Richard Henderson
2020-07-08 22:20 ` [PATCH v3 03/21] softfloat: add xtensa specialization for pickNaNMulAdd Max Filippov
2020-07-09 0:03 ` Richard Henderson
2020-07-08 22:20 ` [PATCH v3 04/21] target/xtensa: add geometry to xtensa_get_regfile_by_name Max Filippov
2020-07-08 22:20 ` [PATCH v3 05/21] target/xtensa: support copying registers up to 64 bits wide Max Filippov
2020-07-08 22:20 ` [PATCH v3 06/21] target/xtensa: rename FPU2000 translators and helpers Max Filippov
2020-07-08 22:20 ` Max Filippov [this message]
2020-07-08 22:20 ` [PATCH v3 08/21] target/xtensa: don't access BR regfile directly Max Filippov
2020-07-08 22:20 ` [PATCH v3 09/21] target/xtensa: add DFP option, registers and opcodes Max Filippov
2020-07-08 22:20 ` [PATCH v3 10/21] target/xtensa: implement FPU division and square root Max Filippov
2020-07-08 22:20 ` [PATCH v3 11/21] tests/tcg/xtensa: fix test execution on ISS Max Filippov
2020-07-08 22:20 ` [PATCH v3 12/21] tests/tcg/xtensa: update test_fp0_arith for DFPU Max Filippov
2020-07-08 22:20 ` [PATCH v3 13/21] tests/tcg/xtensa: expand madd tests Max Filippov
2020-07-08 22:20 ` [PATCH v3 14/21] tests/tcg/xtensa: update test_fp0_conv for DFPU Max Filippov
2020-07-08 22:20 ` [PATCH v3 15/21] tests/tcg/xtensa: update test_fp1 " Max Filippov
2020-07-08 22:20 ` [PATCH v3 16/21] tests/tcg/xtensa: update test_lsc " Max Filippov
2020-07-08 22:20 ` [PATCH v3 17/21] tests/tcg/xtensa: add fp0 div and sqrt tests Max Filippov
2020-07-08 22:20 ` [PATCH v3 18/21] tests/tcg/xtensa: test double precision load/store Max Filippov
2020-07-08 22:20 ` [PATCH v3 19/21] tests/tcg/xtensa: add DFP0 arithmetic tests Max Filippov
2020-07-08 22:21 ` [PATCH v3 20/21] target/xtensa: import de233_fpu core Max Filippov
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