From: Jonathan Marek <jonathan@marek.ca>
To: linux-arm-msm@vger.kernel.org
Cc: Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK),
linux-kernel@vger.kernel.org (open list)
Subject: [PATCH v3 09/14] clk: qcom: add common gdsc_gx_do_nothing_enable for gpucc drivers
Date: Thu, 9 Jul 2020 09:52:40 -0400 [thread overview]
Message-ID: <20200709135251.643-10-jonathan@marek.ca> (raw)
In-Reply-To: <20200709135251.643-1-jonathan@marek.ca>
All gpucc drivers need this, so move it to common code instead of
duplicating it in every gpucc driver.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
drivers/clk/qcom/gdsc.c | 25 +++++++++++++++++++++++++
drivers/clk/qcom/gdsc.h | 1 +
drivers/clk/qcom/gpucc-sc7180.c | 27 +--------------------------
drivers/clk/qcom/gpucc-sdm845.c | 27 +--------------------------
4 files changed, 28 insertions(+), 52 deletions(-)
diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
index 04944f11659b..628397703717 100644
--- a/drivers/clk/qcom/gdsc.c
+++ b/drivers/clk/qcom/gdsc.c
@@ -433,3 +433,28 @@ void gdsc_unregister(struct gdsc_desc *desc)
}
of_genpd_del_provider(dev->of_node);
}
+
+/*
+ * On SDM845+ the GPU GX domain is *almost* entirely controlled by the GMU
+ * running in the CX domain so the CPU doesn't need to know anything about the
+ * GX domain EXCEPT....
+ *
+ * Hardware constraints dictate that the GX be powered down before the CX. If
+ * the GMU crashes it could leave the GX on. In order to successfully bring back
+ * the device the CPU needs to disable the GX headswitch. There being no sane
+ * way to reach in and touch that register from deep inside the GPU driver we
+ * need to set up the infrastructure to be able to ensure that the GPU can
+ * ensure that the GX is off during this super special case. We do this by
+ * defining a GX gdsc with a dummy enable function and a "default" disable
+ * function.
+ *
+ * This allows us to attach with genpd_dev_pm_attach_by_name() in the GPU
+ * driver. During power up, nothing will happen from the CPU (and the GMU will
+ * power up normally but during power down this will ensure that the GX domain
+ * is *really* off - this gives us a semi standard way of doing what we need.
+ */
+int gdsc_gx_do_nothing_enable(struct generic_pm_domain *domain)
+{
+ /* Do nothing but give genpd the impression that we were successful */
+ return 0;
+}
diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h
index c36fc26dcdff..1896bfb2bbd1 100644
--- a/drivers/clk/qcom/gdsc.h
+++ b/drivers/clk/qcom/gdsc.h
@@ -68,6 +68,7 @@ struct gdsc_desc {
int gdsc_register(struct gdsc_desc *desc, struct reset_controller_dev *,
struct regmap *);
void gdsc_unregister(struct gdsc_desc *desc);
+int gdsc_gx_do_nothing_enable(struct generic_pm_domain *domain);
#else
static inline int gdsc_register(struct gdsc_desc *desc,
struct reset_controller_dev *rcdev,
diff --git a/drivers/clk/qcom/gpucc-sc7180.c b/drivers/clk/qcom/gpucc-sc7180.c
index 7b656b6aeced..88a739b6fec3 100644
--- a/drivers/clk/qcom/gpucc-sc7180.c
+++ b/drivers/clk/qcom/gpucc-sc7180.c
@@ -170,37 +170,12 @@ static struct gdsc cx_gdsc = {
.flags = VOTABLE,
};
-/*
- * On SC7180 the GPU GX domain is *almost* entirely controlled by the GMU
- * running in the CX domain so the CPU doesn't need to know anything about the
- * GX domain EXCEPT....
- *
- * Hardware constraints dictate that the GX be powered down before the CX. If
- * the GMU crashes it could leave the GX on. In order to successfully bring back
- * the device the CPU needs to disable the GX headswitch. There being no sane
- * way to reach in and touch that register from deep inside the GPU driver we
- * need to set up the infrastructure to be able to ensure that the GPU can
- * ensure that the GX is off during this super special case. We do this by
- * defining a GX gdsc with a dummy enable function and a "default" disable
- * function.
- *
- * This allows us to attach with genpd_dev_pm_attach_by_name() in the GPU
- * driver. During power up, nothing will happen from the CPU (and the GMU will
- * power up normally but during power down this will ensure that the GX domain
- * is *really* off - this gives us a semi standard way of doing what we need.
- */
-static int gx_gdsc_enable(struct generic_pm_domain *domain)
-{
- /* Do nothing but give genpd the impression that we were successful */
- return 0;
-}
-
static struct gdsc gx_gdsc = {
.gdscr = 0x100c,
.clamp_io_ctrl = 0x1508,
.pd = {
.name = "gx_gdsc",
- .power_on = gx_gdsc_enable,
+ .power_on = gdsc_gx_do_nothing_enable,
},
.pwrsts = PWRSTS_OFF_ON,
.flags = CLAMP_IO,
diff --git a/drivers/clk/qcom/gpucc-sdm845.c b/drivers/clk/qcom/gpucc-sdm845.c
index e40efba1bf7d..5663698b306b 100644
--- a/drivers/clk/qcom/gpucc-sdm845.c
+++ b/drivers/clk/qcom/gpucc-sdm845.c
@@ -131,37 +131,12 @@ static struct gdsc gpu_cx_gdsc = {
.flags = VOTABLE,
};
-/*
- * On SDM845 the GPU GX domain is *almost* entirely controlled by the GMU
- * running in the CX domain so the CPU doesn't need to know anything about the
- * GX domain EXCEPT....
- *
- * Hardware constraints dictate that the GX be powered down before the CX. If
- * the GMU crashes it could leave the GX on. In order to successfully bring back
- * the device the CPU needs to disable the GX headswitch. There being no sane
- * way to reach in and touch that register from deep inside the GPU driver we
- * need to set up the infrastructure to be able to ensure that the GPU can
- * ensure that the GX is off during this super special case. We do this by
- * defining a GX gdsc with a dummy enable function and a "default" disable
- * function.
- *
- * This allows us to attach with genpd_dev_pm_attach_by_name() in the GPU
- * driver. During power up, nothing will happen from the CPU (and the GMU will
- * power up normally but during power down this will ensure that the GX domain
- * is *really* off - this gives us a semi standard way of doing what we need.
- */
-static int gx_gdsc_enable(struct generic_pm_domain *domain)
-{
- /* Do nothing but give genpd the impression that we were successful */
- return 0;
-}
-
static struct gdsc gpu_gx_gdsc = {
.gdscr = 0x100c,
.clamp_io_ctrl = 0x1508,
.pd = {
.name = "gpu_gx_gdsc",
- .power_on = gx_gdsc_enable,
+ .power_on = gdsc_gx_do_nothing_enable,
},
.pwrsts = PWRSTS_OFF_ON,
.flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR,
--
2.26.1
next prev parent reply other threads:[~2020-07-09 13:55 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-09 13:52 [PATCH v3 00/14] Enable GPU for SM8150 and SM8250 Jonathan Marek
2020-07-09 13:52 ` [PATCH v3 01/14] clk: qcom: gcc: fix sm8150 GPU and NPU clocks Jonathan Marek
2020-07-24 8:52 ` Stephen Boyd
2020-07-09 13:52 ` [PATCH v3 02/14] clk: qcom: clk-alpha-pll: remove unused/incorrect PLL_CAL_VAL Jonathan Marek
2020-07-24 8:52 ` Stephen Boyd
2020-07-09 13:52 ` [PATCH v3 03/14] clk: qcom: clk-alpha-pll: same regs and ops for trion and lucid Jonathan Marek
2020-07-24 8:52 ` Stephen Boyd
2020-07-09 13:52 ` [PATCH v3 04/14] clk: qcom: clk-alpha-pll: use the right PCAL_DONE value for lucid pll Jonathan Marek
2020-07-24 8:52 ` Stephen Boyd
2020-07-09 13:52 ` [PATCH v3 05/14] clk: qcom: gcc: remove unnecessary vco_table from SM8150 Jonathan Marek
2020-07-24 8:52 ` Stephen Boyd
2020-07-09 13:52 ` [PATCH v3 06/14] dt-bindings: clock: combine qcom,sdm845-gpucc and qcom,sc7180-gpucc Jonathan Marek
2020-07-13 23:06 ` Rob Herring
2020-07-24 8:52 ` Stephen Boyd
2020-07-09 13:52 ` [PATCH v3 07/14] dt-bindings: clock: add SM8150 QCOM Graphics clock bindings Jonathan Marek
2020-07-13 23:06 ` Rob Herring
2020-07-24 8:52 ` Stephen Boyd
2020-07-09 13:52 ` [PATCH v3 08/14] dt-bindings: clock: add SM8250 " Jonathan Marek
2020-07-13 23:06 ` Rob Herring
2020-07-24 8:52 ` Stephen Boyd
2020-07-09 13:52 ` Jonathan Marek [this message]
2020-07-24 8:52 ` [PATCH v3 09/14] clk: qcom: add common gdsc_gx_do_nothing_enable for gpucc drivers Stephen Boyd
2020-07-09 13:52 ` [PATCH v3 10/14] clk: qcom: Add graphics clock controller driver for SM8150 Jonathan Marek
2020-07-24 8:52 ` Stephen Boyd
2020-07-09 13:52 ` [PATCH v3 11/14] clk: qcom: Add graphics clock controller driver for SM8250 Jonathan Marek
2020-07-24 8:52 ` Stephen Boyd
2020-07-09 13:52 ` [PATCH v3 12/14] dt-bindings: power: Add missing rpmpd rpmh regulator level Jonathan Marek
2020-07-13 23:07 ` Rob Herring
2020-07-09 13:52 ` [PATCH v3 13/14] arm64: dts: qcom: add sm8150 GPU nodes Jonathan Marek
2020-07-09 13:52 ` [PATCH v3 14/14] arm64: dts: qcom: add sm8250 " Jonathan Marek
2020-07-21 7:54 ` [PATCH v3 00/14] Enable GPU for SM8150 and SM8250 Stephen Boyd
2020-07-21 15:45 ` Dmitry Baryshkov
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200709135251.643-10-jonathan@marek.ca \
--to=jonathan@marek.ca \
--cc=agross@kernel.org \
--cc=bjorn.andersson@linaro.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mturquette@baylibre.com \
--cc=sboyd@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.